Cypress CY7C1380DV25, CY7C1382DV25 Maximum Ratings, Operating Range, Electrical Characteristics

CY7C1380DV25, CY7C1380FV25 CY7C1382DV25, CY7C1382FV25

Maximum Ratings

Exceeding the maximum ratings may impair the useful life of the device. For user guidelines, not tested.

Storage Temperature		–65°C to +150°C
Ambient Temperature with
Power Applied		–55°C to +125°C
Supply Voltage on VDD Relative to GND		–0.3V to +3.6V
Supply Voltage on VDDQ Relative to GND		–0.3V to +VDD
DC Voltage Applied to Outputs	–0.5V to VDDQ + 0.5V
in Tri-State

DC Input Voltage	–0.5V to VDD + 0.5V
Current into Outputs (LOW)	20 mA
Static Discharge Voltage	>2001V
(per MIL-STD-883, Method 3015)
Latch-up Current	>200 mA

Operating Range

	Ambient
Range	Temperature	VDD/VDDQ
Commercial	0°C to +70°C	2.5V ± 5%
Industrial	–40°C to +85°C

Electrical Characteristics

Over the Operating Range [16, 17]

Parameter	Description	Test Conditions		Min.	Max.	Unit
VDD	Power Supply Voltage			2.375	2.625	V
VDDQ	IO Supply Voltage	for 2.5V IO		2.375	VDD	V
VOH	Output HIGH Voltage	for 2.5V IO, IOH = −1.0 mA		2.0		V
VOL	Output LOW Voltage	for 2.5V IO, IOL= 1.0 mA			0.4	V
VIH	Input HIGH Voltage [16]	for 2.5V IO		1.7	VDD + 0.3V	V
VIL	Input LOW Voltage [16]	for 2.5V IO		–0.3	0.7	V
IX	Input Leakage Current	GND ≤ VI ≤ VDDQ		–5	5	∝A
	except ZZ and MODE
	Input Current of MODE	Input = VSS		–30		∝A
		Input = VDD			5	∝A
	Input Current of ZZ	Input = VSS		–5		∝A
		Input = VDD			30	∝A
IOZ	Output Leakage Current	GND ≤ VI ≤ VDD, Output Disabled		–5	5	∝A
IDD	VDD Operating Supply	VDD = Max., IOUT = 0 mA,	4.0-ns cycle, 250 MHz		350	mA
	Current	f = fMAX = 1/tCYC
			5.0-ns cycle, 200 MHz		300	mA
			6.0-ns cycle, 167 MHz		275	mA
ISB1	Automatic CE	VDD = Max, Device Deselected,	4.0-ns cycle, 250 MHz		160	mA
	Power Down	VIN ≥ VIH or VIN ≤ VIL
			5.0-ns cycle, 200 MHz		150	mA
	Current—TTL Inputs	f = fMAX = 1/tCYC
			6.0-ns cycle, 167 MHz		140	mA
ISB2	Automatic CE	VDD = Max, Device Deselected,	All speeds		70	mA
	Power Down	VIN ≤ 0.3V or VIN > VDDQ – 0.3V,
	Current—CMOS Inputs	f = 0
ISB3	Automatic CE	VDD = Max, Device Deselected, or	4.0-ns cycle, 250 MHz		135	mA
	Power Down	VIN ≤ 0.3V or VIN > VDDQ – 0.3V
			5.0-ns cycle, 200 MHz		130	mA
	Current—CMOS Inputs	f = fMAX = 1/tCYC
			6.0-ns cycle, 167 MHz		125	mA
ISB4	Automatic CE	VDD = Max, Device Deselected,	All speeds		80	mA
	Power Down	VIN ≥ VIH or VIN ≤ VIL, f = 0
	Current—TTL Inputs

Notes:

16.Overshoot: VIH(AC) < VDD +1.5V (pulse width less than tCYC/2), undershoot: VIL(AC) > –2V (pulse width less than tCYC/2).

17.Tpower up: assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.

Document #: 38-05546 Rev. *E Page 17 of 29

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