CY7C1380DV25, CY7C1380FV25

CY7C1382DV25, CY7C1382FV25

Truth Table [4, 5, 6, 7, 8]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Operation

Add. Used

 

CE1

CE2

 

CE3

ZZ

ADSP

 

 

ADSC

 

ADV

 

 

WRITE

 

OE

 

CLK

DQ

Deselect Cycle, Power Down

None

 

H

X

 

X

L

 

X

 

 

L

 

X

 

 

X

 

X

 

L-H

Tri-State

Deselect Cycle, Power Down

None

 

L

L

 

X

L

 

L

 

 

X

 

X

 

 

X

 

X

 

L-H

Tri-State

Deselect Cycle, Power Down

None

 

L

X

 

H

L

 

L

 

 

X

 

X

 

 

X

 

X

 

L-H

Tri-State

Deselect Cycle, Power Down

None

 

L

L

 

X

L

 

H

 

 

L

 

X

 

 

X

 

X

 

L-H

Tri-State

Deselect Cycle, Power Down

None

 

L

X

 

H

L

 

H

 

 

L

 

X

 

 

X

 

X

 

L-H

Tri-State

Sleep Mode, Power Down

None

 

X

X

 

X

H

 

X

 

 

X

 

X

 

 

X

 

X

 

X

Tri-State

Read Cycle, Begin Burst

External

 

L

H

 

L

L

 

L

 

 

X

 

X

 

 

X

 

L

 

L-H

Q

Read Cycle, Begin Burst

External

 

L

H

 

L

L

 

L

 

 

X

 

X

 

 

X

 

H

 

L-H

Tri-State

Write Cycle, Begin Burst

External

 

L

H

 

L

L

 

H

 

 

L

 

X

 

 

L

 

X

 

L-H

D

Read Cycle, Begin Burst

External

 

L

H

 

L

L

 

H

 

 

L

 

X

 

 

H

 

L

 

L-H

Q

Read Cycle, Begin Burst

External

 

L

H

 

L

L

 

H

 

 

L

 

X

 

 

H

 

H

 

L-H

Tri-State

Read Cycle, Continue Burst

Next

 

X

X

 

X

L

 

H

 

 

H

 

L

 

 

H

 

L

 

L-H

Q

Read Cycle, Continue Burst

Next

 

X

X

 

X

L

 

H

 

 

H

 

L

 

 

H

 

H

 

L-H

Tri-State

Read Cycle, Continue Burst

Next

 

H

X

 

X

L

 

X

 

 

H

 

L

 

 

H

 

L

 

L-H

Q

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle, Continue Burst

Next

 

H

X

 

X

L

 

X

 

 

H

 

L

 

 

H

 

H

 

L-H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Cycle, Continue Burst

Next

 

X

X

 

X

L

 

H

 

 

H

 

L

 

 

L

 

X

 

L-H

D

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Cycle, Continue Burst

Next

 

H

X

 

X

L

 

X

 

 

H

 

L

 

 

L

 

X

 

L-H

D

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle, Suspend Burst

Current

 

X

X

 

X

L

 

H

 

 

H

 

H

 

 

H

 

L

 

L-H

Q

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle, Suspend Burst

Current

 

X

X

 

X

L

 

H

 

 

H

 

H

 

 

H

 

H

 

L-H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle, Suspend Burst

Current

 

H

X

 

X

L

 

X

 

 

H

 

H

 

 

H

 

L

 

L-H

Q

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle, Suspend Burst

Current

 

H

X

 

X

L

 

X

 

 

H

 

H

 

 

H

 

H

 

L-H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Cycle, Suspend Burst

Current

 

X

X

 

X

L

 

H

 

 

H

 

H

 

 

L

 

X

 

L-H

D

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Cycle, Suspend Burst

Current

 

H

X

 

X

L

 

X

 

 

H

 

H

 

 

L

 

X

 

L-H

D

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Notes:

4.X = Don't Care, H = Logic HIGH, L = Logic LOW.

5.WRITE = L when any one or more byte write enable signals, and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H.

6.The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

7.The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't care for the remainder of the write cycle

8.OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are Tri-State when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).

Document #: 38-05546 Rev. *E

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Cypress CY7C1380DV25, CY7C1382DV25, CY7C1380FV25, CY7C1382FV25 manual Operation Add. Used, CE1 CE2 CE3 Adsp Adsc ADV Write CLK

CY7C1382DV25, CY7C1380DV25, CY7C1382FV25, CY7C1380FV25 specifications

The Cypress CY7C1380FV25, CY7C1382FV25, CY7C1380DV25, and CY7C1382DV25 are high-performance static random access memory (SRAM) devices distinguished by their reliability and efficiency. These components are designed for applications requiring fast data storage and retrieval, making them ideal for embedded systems, communication devices, and various consumer electronics.

One of the main features of these SRAMs is their access time. The CY7C1380FV25 and CY7C1382FV25 models come with a super-fast access time of 25 nanoseconds, ensuring that data can be retrieved with minimal delay. This characteristic is crucial for high-speed applications, such as networking equipment and automotive systems, where rapid data processing is essential.

Both families of devices offer a competitive data width configuration, with CY7C1380 series providing 8 bits and CY7C1382 series providing 16 bits. This flexibility allows designers to choose the appropriate configuration based on their specific application requirements. Additionally, they support a wide voltage range for ease of integration into various systems.

The CY7C1380FV25 and CY7C1380DV25 devices feature low power consumption, which is vital for battery-operated devices. With their advanced CMOS technology, they exhibit reduced static power requirements, helping to prolong battery life and improve overall system efficiency. The IDD (supply current) ratings are particularly low, making them suitable for energy-sensitive applications.

A notable characteristic of the Cypress memory devices is their asynchronous read and write operations, providing simple interfacing in a variety of designs. They are designed to operate under a wide range of temperature conditions; thus, they are well-suited for industrial applications where temperature fluctuations might be a concern.

Furthermore, the CY7C1382FV25 and CY7C1382DV25 models include features like burst mode capability, enabling faster sequential access, which is beneficial for high-speed data processing tasks. This allows these SRAMs to deliver enhanced performance critical in applications like video processing and real-time data acquisition.

In summary, the Cypress CY7C1380FV25, CY7C1382FV25, CY7C1380DV25, and CY7C1382DV25 are distinguished by their fast access times, low power consumption, and flexible data widths. Their advanced technologies and characteristics make them a reliable choice for a diverse range of high-performance applications, ensuring that engineers can effectively address their design challenges while meeting the demands of modern electronics.