Cypress CY7C1380DV25, CY7C1382DV25 manual TAP Timing, TAP AC Switching Characteristics, Hold Times

CY7C1380DV25, CY7C1380FV25 CY7C1382DV25, CY7C1382FV25

instruction. When HIGH, it will enable the output buffers to drive the output bus. When LOW, this bit will place the output bus into a High-Z condition.

This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the Shift-DR state. During Update-DR, the value loaded into that shift-register cell will latch into the preload register. When the EXTEST instruction is entered, this bit will

directly control the output Q-bus pins. Note that this bit is preset HIGH to enable the output when the device is powered up, and also when the TAP controller is in the Test-Logic-Reset state.

Reserved

These instructions are not implemented but are reserved for future use. Do not use these instructions.

TAP Timing

1	2
Test Clock
(TCK)	tTH
tTMSS	tTMSH
Test Mode Select
(TMS)
tTDIS	tTDIH
Test Data-In
(TDI)
Test Data-Out
(TDO)

3

tTL tCYC

4 5 6

tTDOV

tTDOX

DON’T CARE

UNDEFINED

TAP AC Switching Characteristics

Over the Operating Range [10, 11]

Parameter	Description	Min.	Max.	Unit
Clock
tTCYC	TCK Clock Cycle Time	50		ns
tTF	TCK Clock Frequency		20	MHz
tTH	TCK Clock HIGH time	20		ns
tTL	TCK Clock LOW time	20		ns
Output Times
tTDOV	TCK Clock LOW to TDO Valid		10	ns
tTDOX	TCK Clock LOW to TDO Invalid	0		ns
Setup Times
tTMSS	TMS Setup to TCK Clock Rise	5		ns
tTDIS	TDI Setup to TCK Clock Rise	5		ns
tCS	Capture Setup to TCK Rise	5		ns
Hold Times
tTMSH	TMS Hold after TCK Clock Rise	5		ns
tTDIH	TDI Hold after Clock Rise	5		ns
tCH	Capture Hold after Clock Rise	5		ns

Notes:

10.tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.

11.Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1ns.

Document #: 38-05546 Rev. *E Page 13 of 29

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