Cypress CY7C1382FV25 Switching Characteristics, MHz 200 MHz 167 MHz Parameter Description Min

CY7C1380DV25, CY7C1380FV25

CY7C1382DV25, CY7C1382FV25

Switching Characteristics

Over the Operating Range [19, 20]

												250 MHz		200 MHz		167 MHz
	Parameter										Description	Min.	Max	Min.	Max.	Min.	Max	Unit
t	POWER	V (Typical) to the First Access [21]										1		1		1		ms
		DD
Clock
tCYC		Clock Cycle Time										4.0		5		6		ns
tCH		Clock HIGH										1.7		2.0		2.2		ns
tCL		Clock LOW										1.7		2.0		2.2		ns
Output Times
tCO		Data Output Valid After CLK Rise											2.6		3.0		3.4	ns
tDOH		Data Output Hold After CLK Rise										1.0		1.3		1.3		ns
tCLZ		Clock to Low-Z [22, 23, 24]										1.0		1.3		1.3		ns
tCHZ		Clock to High-Z [22, 23, 24]											2.6		3.0		3.4	ns
tOEV			LOW to Output Valid										2.6		3.0		3.4	ns
		OE
tOELZ			LOW to Output Low-Z [22, 23, 24]									0		0		0		ns
		OE
tOEHZ			HIGH to Output High-Z [22, 23, 24]										2.6		3.0		3.4	ns
		OE
Setup Times
tAS		Address Setup Before CLK Rise										1.2		1.4		1.5		ns
tADS										Setup Before CLK Rise		1.2		1.4		1.5		ns
		ADSC,					ADSP
tADVS					Setup Before CLK Rise							1.2		1.4		1.5		ns
		ADV
tWES											X Setup Before CLK Rise	1.2		1.4		1.5		ns
		GW,			BWE,			BW
tDS		Data Input Setup Before CLK Rise										1.2		1.4		1.5		ns
tCES		Chip Enable Setup Before CLK Rise										1.2		1.4		1.5		ns
Hold Times
tAH		Address Hold After CLK Rise										0.3		0.4		0.5		ns
tADH									Hold After CLK Rise			0.3		0.4		0.5		ns
		ADSP,				ADSC
tADVH				Hold After CLK Rise								0.3		0.4		0.5		ns
		ADV
tWEH											X Hold After CLK Rise	0.3		0.4		0.5		ns
		GW,			BWE,			BW
tDH		Data Input Hold After CLK Rise										0.3		0.4		0.5		ns
tCEH		Chip Enable Hold After CLK Rise										0.3		0.4		0.5		ns

Notes:

19.Timing reference level is 1.5V when VDDQ = 1.25V when VDDQ = 2.5V.

20.Test conditions shown in (a) of AC Test Loads unless otherwise noted.

21.This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation can be initiated.

22.tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.

23.At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions.

24.This parameter is sampled and not 100% tested.

Document #: 38-05546 Rev. *E Page 19 of 29

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