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Cypress CY7C1386D, CY7C1386F, CY7C1387D, CY7C1387F Switching Waveforms

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CY7C1386D, CY7C1386F

CY7C1387D, CY7C1387F

Document Number: 38-05545 Rev. *E Page 21 of 30

Switching Waveforms

Read Cycle Timing [26]

tCYC

tCL

CLK

ADSP

tADH

tADS

ADDRESS

tCH

ADSC

tAH

tAS

tCEH

tCES

GW, BWE,BW

Data Out (DQ) High-Z

tDOH

tCO

ADV

tOEHZ

tCO

Single READ BURST READ

tOEV

tOELZ tCHZ

Burst wraps around

to its initial state

tADVH

tADVS

tWEH

tWES

tADH

tADS

Q(A2)

Q(A2 + 1)

Q(A2 + 2)

Q(A1) Q(A2)

Q(A2 + 1)

Q(A3)

Q(A2 + 3)

A2 A3

Deselect

cycle

Burst continued with

new base address

ADV suspends burst

DON’T CARE UNDEFINED

CLZ

Note

26.On this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

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Contents

Main 18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Features Functional Description Selection Guide Logic Block Diagram CY7C1386D/CY7C1386F [3] (512K x 36) Logic Block Diagram CY7C1387D/CY7C1387F E PIPELINED ENABLE OUTPUT REGISTERS INPUT REGISTERS CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Document Number: 38-05545 Rev. *E Page 3 of 30 Pin Configurations CY7C1386D (512K X 36) CY7C1387D (1M x 18) Pin Configurations CY7C1386F (512K x 36) CY7C1387F (1M x 18) 119-Ball BGA Pinout (1 Chip Enable) Pin Configurations 165-Ball FBGA Pinout (3 Chip Enable) CY7C1386D (512K x 36) CY7C1387D (1M x 18) 2345671 A B C D E F G H J K L M N P R 891011 CY7C1386D, CY7C1386F Pin Definitions CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Functional Overview Pin Definitions CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Interleaved Burst Address Table (MODE = Floating or VDD) Linear Burst Address Table (MODE = GND) ZZ Mode Electrical Characteristics Truth Table Truth Table for Read/Write Truth Table for Read/Write IEEE 1149.1 Serial Boundary Scan (JTAG) TAP Controller State Diagram TAP Controller Block Diagram Page CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F TAP Ti min g TAP AC Switching Characteristics 3.3V TAP AC Test Conditions 3.3V TAP AC Output Load Equivalent 2.5V TAP AC Test Conditions 2.5V TAP AC Output Load Equivalent TAP DC Electrical Characteristics And Operating Conditions Identification Register Definitions Scan Register Sizes Identification Codes 119-Ball BGA Boundary Scan Order[14, 15] 165-Ball BGA Boundary Scan Order[14, 16] Maximum Ratings Operating Range Electrical Characteristics Capacitance Thermal Resistance AC Test Loads and Waveforms Switching Characteristics Switching Waveforms Read Cycle Timing Write Cycle Timing Read/Write Cycle Timing ZZ Mode Timing Page Ordering Information Package Diagrams Figure 1. 100-Pin Thin Plastic Quad Flat pack (14 x 20 x 1.4 mm) (51-85050) A Page Figure 3. 165-Ball FBGA (13 x 15 x 1.4 mm) (51-85180) SOLDERPAD TYPE : NON-SOLDER MASK DEFINED (NSMD) 1.40MAX. 51-85180-*A Package Diagrams - NOTES : PACKAGE WEIGHT : 0.475g JEDEC REFERENCE : MO-216 / DESIGN 4.6C PACKAGE CODE : BB0AC NOTES: PACKAGEWEIGHT : 0.475g JEDECREFERENCE : MO-216 / DESIGN 4.6C PACKAGECODE : BB0AC 51-85180-*A Document History Page