Cypress CY7C1386D, CY7C1386F, CY7C1387D, CY7C1387F Write Cycle Timing

CY7C1386D, CY7C1386F

CY7C1387D, CY7C1387F

Document Number: 38-05545 Rev. *E Page 22 of 30

Write Cycle Timing [26, 27]

Switching Waveforms (continued)

tCYC

tCL

CLK

ADSP

tADH

tADS

ADDRESS

tCH

ADSC

tAH

tAS

tCEH

tCES

BWE,

BWX

ADV

BURST READ BURST WRITE

D(A2)

D(A2 + 1)

D(A3)

D(A3 + 1)

D(A2 + 3)

A2 A3

Extended BURST WRITE

Single WRITE

tADH

tADS

tADH

tADS

OEHZ

tADVH

tADVS

tWEH

tWES

tDS

tWEH

tWES

Byte write signals are ignored for ﬁrst cycle when

ADSP initiates burst

ADSC extends burst

ADV suspends burst

DON’T CARE UNDEFINED

D(A1)

High-Z

Data in (D)

Data Out (Q)

Note

27.Full width write can be initiated by either GW LOW, or by GW HIGH, BWE LOW, and BWX LOW.

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Contents

Main 18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Features Functional Description Selection Guide Logic Block Diagram CY7C1386D/CY7C1386F [3] (512K x 36) Logic Block Diagram CY7C1387D/CY7C1387F E PIPELINED ENABLE OUTPUT REGISTERS INPUT REGISTERS CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Document Number: 38-05545 Rev. *E Page 3 of 30 Pin Configurations CY7C1386D (512K X 36) CY7C1387D (1M x 18) Pin Configurations CY7C1386F (512K x 36) CY7C1387F (1M x 18) 119-Ball BGA Pinout (1 Chip Enable) Pin Configurations 165-Ball FBGA Pinout (3 Chip Enable) CY7C1386D (512K x 36) CY7C1387D (1M x 18) 2345671 A B C D E F G H J K L M N P R 891011 CY7C1386D, CY7C1386F Pin Definitions CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Functional Overview Pin Definitions CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Interleaved Burst Address Table (MODE = Floating or VDD) Linear Burst Address Table (MODE = GND) ZZ Mode Electrical Characteristics Truth Table Truth Table for Read/Write Truth Table for Read/Write IEEE 1149.1 Serial Boundary Scan (JTAG) TAP Controller State Diagram TAP Controller Block Diagram Page CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F TAP Ti min g TAP AC Switching Characteristics 3.3V TAP AC Test Conditions 3.3V TAP AC Output Load Equivalent 2.5V TAP AC Test Conditions 2.5V TAP AC Output Load Equivalent TAP DC Electrical Characteristics And Operating Conditions Identification Register Definitions Scan Register Sizes Identification Codes 119-Ball BGA Boundary Scan Order[14, 15] 165-Ball BGA Boundary Scan Order[14, 16] Maximum Ratings Operating Range Electrical Characteristics Capacitance Thermal Resistance AC Test Loads and Waveforms Switching Characteristics Switching Waveforms Read Cycle Timing Write Cycle Timing Read/Write Cycle Timing ZZ Mode Timing Page Ordering Information Package Diagrams Figure 1. 100-Pin Thin Plastic Quad Flat pack (14 x 20 x 1.4 mm) (51-85050) A Page Figure 3. 165-Ball FBGA (13 x 15 x 1.4 mm) (51-85180) SOLDERPAD TYPE : NON-SOLDER MASK DEFINED (NSMD) 1.40MAX. 51-85180-*A Package Diagrams - NOTES : PACKAGE WEIGHT : 0.475g JEDEC REFERENCE : MO-216 / DESIGN 4.6C PACKAGE CODE : BB0AC NOTES: PACKAGEWEIGHT : 0.475g JEDECREFERENCE : MO-216 / DESIGN 4.6C PACKAGECODE : BB0AC 51-85180-*A Document History Page