CY7C1470BV25
CY7C1472BV25, CY7C1474BV25
Table 4. Truth Table
The truth table for CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25 follows. [1, 2, 3, 4, 5, 6, 7]
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Operation | CE |
| ZZ | ADV/LD |
| WE |
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| BWx |
| OE |
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| CEN |
| CLK | DQ | |||||
Used |
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Deselect Cycle | None |
| H |
| L | L |
| X |
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| X |
| X |
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| L |
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Continue Deselect Cycle | None |
| X |
| L | H |
| X |
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| X |
| X |
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| L |
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Read Cycle | External |
| L |
| L | L |
| H |
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| X |
| L |
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| L |
| Data Out (Q) | ||||
(Begin Burst) |
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Read Cycle | Next |
| X |
| L | H |
| X |
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| X |
| L |
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| L |
| Data Out (Q) | ||||
(Continue Burst) |
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NOP/Dummy Read | External |
| L |
| L | L |
| H |
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| X |
| H |
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| L |
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(Begin Burst) |
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Dummy Read | Next |
| X |
| L | H |
| X |
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| X |
| H |
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| L |
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(Continue Burst) |
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Write Cycle | External |
| L |
| L | L |
| L |
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| L |
| X |
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| L |
| Data In (D) | ||||
(Begin Burst) |
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Write Cycle | Next |
| X |
| L | H |
| X |
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| L |
| X |
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| L |
| Data In (D) | ||||
(Continue Burst) |
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NOP/Write Abort | None |
| L |
| L | L |
| L |
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| H |
| X |
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| L |
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(Begin Burst) |
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Write Abort | Next |
| X |
| L | H |
| X |
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| H |
| X |
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| L |
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(Continue Burst) |
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Ignore Clock Edge (Stall) | Current |
| X |
| L | X |
| X |
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| X |
| X |
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| H |
| – | ||||
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Sleep Mode | None |
| X |
| H | X |
| X |
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| X |
| X |
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| X |
| X | ||||
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Notes
1.X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired Byte Write Selects are asserted, see “Partial Write Cycle Description” on page 11 for details.
2.Write is defined by WE and BW[a:d]. See “Partial Write Cycle Description” on page 11 for details.
3.When a write cycle is detected, all IOs are
4.The DQ and DQP pins are controlled by the current cycle and the OE signal.
5.CEN = H inserts wait states.
6.Device powers up deselected with the IOs in a
7.OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles.During a Read cycle DQs and DQP[a:d] =
Document #: | Page 10 of 29 |
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