CY7C1470BV25

CY7C1472BV25, CY7C1474BV25

Table 4. Truth Table

The truth table for CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25 follows. [1, 2, 3, 4, 5, 6, 7]

 

Address

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Operation

CE

 

ZZ

ADV/LD

 

WE

 

 

BWx

 

OE

 

 

CEN

 

CLK

DQ

Used

 

 

 

 

 

 

 

 

 

Deselect Cycle

None

 

H

 

L

L

 

X

 

 

X

 

X

 

 

L

 

L-H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Continue Deselect Cycle

None

 

X

 

L

H

 

X

 

 

X

 

X

 

 

L

 

L-H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle

External

 

L

 

L

L

 

H

 

 

X

 

L

 

 

L

 

L-H

Data Out (Q)

(Begin Burst)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle

Next

 

X

 

L

H

 

X

 

 

X

 

L

 

 

L

 

L-H

Data Out (Q)

(Continue Burst)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NOP/Dummy Read

External

 

L

 

L

L

 

H

 

 

X

 

H

 

 

L

 

L-H

Tri-State

(Begin Burst)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Dummy Read

Next

 

X

 

L

H

 

X

 

 

X

 

H

 

 

L

 

L-H

Tri-State

(Continue Burst)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Cycle

External

 

L

 

L

L

 

L

 

 

L

 

X

 

 

L

 

L-H

Data In (D)

(Begin Burst)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Cycle

Next

 

X

 

L

H

 

X

 

 

L

 

X

 

 

L

 

L-H

Data In (D)

(Continue Burst)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NOP/Write Abort

None

 

L

 

L

L

 

L

 

 

H

 

X

 

 

L

 

L-H

Tri-State

(Begin Burst)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Abort

Next

 

X

 

L

H

 

X

 

 

H

 

X

 

 

L

 

L-H

Tri-State

(Continue Burst)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Ignore Clock Edge (Stall)

Current

 

X

 

L

X

 

X

 

 

X

 

X

 

 

H

 

L-H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Sleep Mode

None

 

X

 

H

X

 

X

 

 

X

 

X

 

 

X

 

X

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Notes

1.X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired Byte Write Selects are asserted, see “Partial Write Cycle Description” on page 11 for details.

2.Write is defined by WE and BW[a:d]. See “Partial Write Cycle Description” on page 11 for details.

3.When a write cycle is detected, all IOs are tri-stated, even during Byte Writes.

4.The DQ and DQP pins are controlled by the current cycle and the OE signal.

5.CEN = H inserts wait states.

6.Device powers up deselected with the IOs in a tri-state condition, regardless of OE.

7.OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles.During a Read cycle DQs and DQP[a:d] = tri-state when OE is inactive or when the device is deselected, and DQs = data when OE is active.

Document #: 001-15032 Rev. *D

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Cypress CY7C1472BV25, CY7C1474BV25, CY7C1470BV25 manual Truth Table, Address Operation, Used