CY7C1470BV25
CY7C1472BV25, CY7C1474BV25
Document #: 001-15032 Rev. *D Page 20 of 29
ISB3 Automatic CE
Power Down
Current—CMOS Inputs
Max. VDD, Device Deselected,
VIN ≤ 0.3V or
VIN > VDDQ − 0.3V,
f = fMAX = 1/tCYC
4.0-ns cycle, 250 MHz 200 mA
5.0-ns cycle, 200 MHz 200 mA
6.0-ns cycle, 167 MHz 200 mA
ISB4 Automatic CE
Power Down
Current—TTL Inputs
Max. VDD, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL, f = 0 All speed grades 135 mA
Electrical Characteristics
Over the Operating Range[12, 13] (continued)
Parameter Description Test Conditions Min Max Unit
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter Description Test Conditions 100 TQFP
Max 165 FBGA
Max 209 FBGA
Max Unit
CADDRESS Address Input Capacitance TA = 25°C, f = 1 MHz,
VDD = 2.5V
VDDQ = 2.5V
6 6 6 pF
CDATA Data Input Capacitance 5 5 5 pF
CCTRL Control Input Capacitance 8 8 8 pF
CCLK Clock Input Capacitance 6 6 6 pF
CIO Input/Output Capacitance 5 5 5 pF
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
Parameter Description Test Conditions 100 TQFP
Package 165 FBGA
Package 209 FBGA
Package Unit
ΘJA Thermal Resistance
(Junction to Ambient) Test conditions follow standard test
methods and procedures for
measuring thermal impedance, per
EIA/JESD51.
24.63 16.3 15.2 °C/W
ΘJC Thermal Resistance
(Junction to Case) 2.28 2.1 1.7 °C/W
AC Test Loads and Waveforms
OUTPUT
R = 1667Ω
R = 1538Ω
5pF
INCLUDING
JIG AND
SCOPE
(a) (b)
OUTPUT
RL= 50Ω
Z0= 50Ω
VL= 1.25V
2.5V ALL INPUT PULSES
VDDQ
GND
90%
10% 90%
10%
≤1 ns ≤1 ns
(c)
2.5V IO Test Load
[+] Feedback