CY7C1470BV25
CY7C1472BV25, CY7C1474BV25
Document History Page
Document Title: CY7C1470BV25/CY7C1472BV25/CY7C1474BV25, 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL™ Architecture
Document Number: 001-15032
REV. | ECN No. | Issue Date | Orig. of Change | Description of Change |
** | 1032642 | See ECN | VKN/KKVTMP | New data sheet |
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*A | 1562503 | See ECN | VKN/AESA | Removed 1.8V IO offering from the data sheet |
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*B | 1897447 | See ECN | VKN/AESA | Added footnote 14 related to IDD |
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*C | 2082487 | See ECN | VKN | Converted from preliminary to final |
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*D | 2159486 | See ECN | VKN/PYRS | Minor Change-Moved to the external web |
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Document #: 001-15032 Rev. *D | Revised February 29, 2008 | Page 29 of 29 |
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc. All products and company names mentioned in this document may be the trademarks of their respective holders.