CY7C1470BV25CY7C1472BV25, CY7C1474BV25

Document #: 001-15032 Rev. *D Page 2 of 29

Logic Block Diagram – CY7C1470BV25 (2M x 36)

Logic Block Diagram – CY7C1472BV25 (4M x 18)

A0,A1, ACMODEBW
a
BW
b
WECE1CE2CE3OE
READLOGIC
DQ
s
DQ
P
a
DQ
P
b
DQ
P
c
DQ
P
d
D
A
T
A
S
T
E
E
R
I
N
G
O
U
TP
U
TB
U
FFERS
MEMORY
ARRAY
E
E
INPUT
REGISTER0
ADDRESS
REGISTER0
WRITEADDRESS
REGISTER1
WRITEADDRESS
REGISTER2
WRITEREGISTRY
ANDDATA COHERENCY
CONTROLLOGIC
BURST
LOGIC
A0'
A1'
D1
D0
Q1
Q0
A0
A1
C
ADV/LD
ADV/LD
E
INPUT
REGISTER1
S
E
N
S
E
A
M
P
S
E
C
LK
C
EN
WRITE
DRIVERS
BW
c
BW
d
ZZ
SLEEPCONTROLOU
T
PU
T
REGIS
T
ERS
A0,A1, ACMODEBW
a
BW
b
WECE1CE2CE3OE
READLOGIC
DQ
s
DQ
P
a
DQ
P
b
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
MEMORY
ARRAY
E
E
INPUT
REGISTER0
ADDRESS
REGISTER0
WRITEADDRESS
REGISTER1
WRITEADDRESS
REGISTER2
WRITEREGISTRY
ANDDATA COHERENCY
CONTROLLOGIC
BURST
LOGIC
A0'
A1'
D1
D0
Q1
Q0
A0
A1
C
ADV/LD
ADV/LD
E
INPUT
REGISTER1
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
C
LK
C
EN
WRITE
DRIVERS
ZZ Sleep
Control
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