CY7C1470BV25
CY7C1472BV25, CY7C1474BV25
Document #: 001-15032 Rev. *D Page 16 of 29
2.5V TAP AC Test Conditions
Input pulse levels.................................................VSS to 2.5V
Input rise and fall time..................................................... 1 ns
Input timing reference levels.........................................1.25V
Output reference levels................................................ 1.25V
Test load termination supply voltage............................1.25V
Note
11.All voltages refer to VSS (GND).
Figure 5. 2.5V TAP AC Output Load Equivalent

TDO

1.25V

20pF

Z = 50Ω

O

50Ω

TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; VDD = 2.5V ±0.125V unless otherwise noted)[11]
Parameter Description Test Conditions Min Max Unit
VOH1 Output HIGH Voltage IOH = –1.0 mA, VDDQ = 2.5V 1.7 V
VOH2 Output HIGH Voltage IOH = –100 μA, VDDQ = 2.5V 2.1 V
VOL1 Output LOW Voltage IOL = 1.0 mA, VDDQ = 2.5V 0.4 V
VOL2 Output LOW Voltage IOL = 100 μA, VDDQ = 2.5V 0.2 V
VIH Input HIGH Voltage VDDQ = 2.5V 1.7 VDD + 0.3 V
VIL Input LOW Voltage VDDQ = 2.5V –0.3 0.7 V
IXInput Load Current GND ≤ VI ≤ VDDQ –5 5 μA
Table 6. Identification Register Definitions
Instruction Field CY7C14 70BV25
(2M x 36) CY7C1472BV25
(4M x 18) CY7C1474BV25
(1M x 72) Description
Revision Number (31:29) 000 000 000 Describes the version number
Device Depth (28:24) 01011 01011 01011 Reserved for internal use
Architecture/Memory Type(23:18) 001000 001000 001000 Defines memory type and archi-
tecture
Bus Width/Density(17:12) 100100 010100 110100 Defines width and density
Cypress JEDEC ID Code (11:1) 00000110100 00000110100 00000110100 Allows unique identification of
SRAM vendor
ID Register Presence Indicator (0) 1 1 1 Indicates the presence of an ID
register
Table 7. Scan Register Sizes
Register Name Bit Size (x36) Bit Size (x18) Bit Size (x72)
Instruction 3 3 3
Bypass 1 1 1
ID 32 32 32
Boundary Scan Order–165FBGA 71 52 –
Boundary Scan Order–209BGA – – 110
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