NOP, Stall and Deselect Cycles | Cypress CY7C1470BV25, CY7C1474BV25

CY7C1470BV25

CY7C1472BV25, CY7C1474BV25

Switching Waveforms (continued)

Figure 7 shows NOP, STALL and DESELECT Cycles waveform.[19, 20, 22]

Figure 7. NOP, STALL and DESELECT Cycles

	1	2	3	4	5	6	7	8	9	10
CLK
CEN
CE
ADV/LD
WE
BWx
ADDRESS	A1	A2		A3	A4			A5
										tCHZ
Data				D(A1)	Q(A2)		Q(A3)	D(A4)		Q(A5)

In-Out (DQ)

WRITE	READ	STALL
D(A1)	Q(A2)

Figure 8 shows ZZ Mode timing waveform.[23, 24]

READ	WRITE	STALL	NOP	READ
Q(A3)	D(A4)			Q(A5)

DON’T CARE

UNDEFINED

Figure 8. ZZ Mode Timing

DESELECT

CONTINUE DESELECT

CLK

ZZ

ISUPPLY

ALL INPUTS (except ZZ)

tZZ

t ZZI

I DDZZ

t ZZREC

t RZZI

DESELECT or READ Only

Outputs (Q)

High-Z

DON’T CARE

Notes

22.The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle.

23.Device must be deselected when entering ZZ mode. See “Truth Table” on page 10 for all possible signal conditions to deselect the device.

24.IOs are in High-Z when exiting ZZ sleep mode.

Document #: 001-15032 Rev. *D

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Cypress CY7C1470BV25, CY7C1474BV25, CY7C1472BV25 manual NOP, Stall and Deselect Cycles

Contents

Description 250 MHz 200 MHz 167 MHz Unit FeaturesFunctional Description Selection Guide Logic Block Diagram CY7C1472BV25 4M x Logic Block Diagram CY7C1470BV25 2M x ADV/LD Logic Block Diagram CY7C1474BV25 1M x Pin Tqfp Pinout Pin Configurations Mode CENNC/1G CE2 CLK TDI TDO Ball Fbga 14 x 22 x 1.76 mm Pinout CY7C1474BV25 1M × TDI Pin Definitions Pin Name IO Type Pin DescriptionADV/LD Dqpx Functional Overview Parameter Description Test Conditions Min Max Unit ZZ Mode Electrical CharacteristicsBurst Write Accesses Used Truth TableAddress Operation Function CY7C1474BV25 Partial Write Cycle DescriptionFunction CY7C1470BV25 Function CY7C1472BV25 Ieee 1149.1 Serial Boundary Scan Jtag TAP Controller State Diagram TAP Instruction Set TAP Timing Hold Times TAP AC Switching CharacteristicsParameter Description Min Max Unit Clock Scan Register Sizes Register Name Bit Size TAP DC Electrical Characteristics And Operating Conditions5V TAP AC Test Conditions GND ≤ VI ≤ Vddq Boundary Scan Exit Order 2M x Bit # Ball ID Identification Codes Instruction Description 10 R1 11 R2 12 R3 13 P2 Boundary Scan Exit Order 4M xBoundary Scan Exit Order 1M x Bit # Ball ID Range Ambient Electrical CharacteristicsMaximum Ratings Operating Range Parameter Description Test Conditions Tqfp Fbga Unit CapacitanceThermal Resistance AC Test Loads and Waveforms Output Times Switching CharacteristicsSetup Times Parameter Description 250 200 167 Unit Min Max A3 A4 Switching WaveformsADV/LD Address Data NOP, Stall and Deselect Cycles Ordering Information 250 Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package Diagrams Ball Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm Document History ECN No Issue Date Orig. of Change Description of Change