Contents
Main
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture
CY7C1470BV25 CY7C1472BV25, CY7C1474BV25
Features
Functional Description
Selection Guide
CY7C1470BV25 CY7C1472BV25, CY7C1474BV25
Document #: 001-15032 Rev. *D Page 2 of 29
Logic Block Diagram CY7C1470BV25 (2M x 36)
C
ADV/LD
Logic Block Diagram CY7C1474BV25 (1M x 72)
ZZ
ADV/LD
A0,A1, A C
MODE
CY7C1470BV25 CY7C1472BV25, CY7C1474BV25
Pin Configurations
(2M 36) (4M 18)
MODE
CY7C1472BV25
CY7C1470BV25 CY7C1472BV25, CY7C1474BV25
Pin Configurations
NC/288M
CY7C1472BV25 (4M x 18)
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1470BV25 (2M x 36)
Pin Configurations
CY7C1474BV25 (1M 72)
209-Ball FBGA (14 x 22 x 1.76 mm) Pinout
A B C D E F G H J K L M N P R T U V W
123456789 1110
CY7C1470BV25 CY7C1472BV25, CY7C1474BV25
Functional Overview
Single Read Accesses
Burst Read Accesses
Single Write Accesses
Sleep Mode
ZZ Mode Electrical Characteristics
Page
Page
IEEE 1149.1 Serial Boundary Scan (JTAG)
Disabling the JTAG Feature
Test Access Port (TAP)
Performing a TAP Reset
TAP Registers
TAP Instruction Set
CY7C1470BV25 CY7C1472BV25, CY7C1474BV25
TAP AC Switching Characteristics
2.5V TAP AC Test Conditions
TDO
1.25V 20pF
50
Z = 50
Page
Boundary Scan Exit Order (4M x 18)
Boundary Scan Exit Order (1M x 72)
Maximum Ratings
Operating Range
Electrical Characteristics
Capacitance
Thermal Resistance
AC Test Loads and Waveforms
Switching Characteristics
Switching Waveforms
Figure 6 shows read-write timing waveform.[19, 20, 21] Figure 6. Read/Write Timing
OE
n-Out (DQ)
BW
Switching Waveforms
I
CLK ZZ
A
LL INPUTS (except ZZ)
Ordering Information
CY7C1470BV25 CY7C1472BV25, CY7C1474BV25
Ordering Information
Package Diagrams
Figure 9. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm), 51-85050
A
Figure 10. 165-Ball FBGA (15 x 17 x 1.4 mm), 51-85165
Package Diagrams
51-85165-*A
Page
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