Manuals / Cypress / Computer Equipment / Clock

Cypress CYV15G0104TRB Biststart BISTSTA, RXDA0, RXDA1 = Bistwait, Bistdatacompare 000, Bisterror

Models: CYV15G0104TRB

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	CYV15G0104TRB
Monitor Data	Receive BIST
Received {BISTSTA, RXDA[0],	Detected LOW RX PLL
RXDA[1]} =	Out of Lock
BIST_START (101)

{BISTSTA, RXDA[0], RXDA[1]} =

BIST_WAIT (111)

	Start of
No	BIST Detected

Yes, {BISTSTA, RXDA[0], RXDA[1]} =

BIST_DATA_COMPARE (000, 001)

Compare

Next Character

	Mismatch
		Match	{BISTSTA, RXDA[0], RXDA[1]} =
Yes	Auto-Abort	Match	BIST_DATA_COMPARE (000, 001)
	Auto-Abort
	Condition
	Condition
	No
	End-of-BIST	End-of-BIST	No
	State	State

	Yes, {BISTSTA, RXDA[0], RXDA[1]} =	Yes, {BISTSTA, RXDA[0], RXDA[1]} =
	BIST_LAST_BAD (100)
		BIST_LAST_GOOD (010)

No, {BISTSTA, RXDA[0], RXDA[1]} =

BIST_ERROR (110)

Figure 2. Receive BIST State Machine

Document #: 38-02100 Rev. *B

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Cypress CYV15G0104TRB manual Biststart BISTSTA, RXDA0, RXDA1 = Bistwait, Bistdatacompare 000, Bistlastbad, Bistlastgood

Contents

Features Functional DescriptionReceive RX channel of the CYV15G0104TRB HOTLink North First Street San Jose, CA Document # 38-02100 Rev. *BROUTA1 ± ROUTA2 ± TOUTB1 ± TOUTB2 ±Reclocking Deserializer Path Block Diagram Serializer Path Block DiagramDevice Configuration and Control Block Diagram JtagPin Configuration Top View1 Pin Configuration Bottom View1 20 19 18 17 16Transmit Path Clock Signals Receive Path Data and Status SignalsReceive Path Clock Signals Name Characteristics Signal DescriptionDevice Control Signals Device Configuration and Control Bus Signals Internal Device Configuration LatchesSignal Detect Amplitude Select Receive Channel Power ControlCYV15G0104TRB HOTLink II Operation CYV15G0104TRB Transmit Data PathREFCLKB± CYV15G0104TRB Receive Data PathSpdselb Txrateb Signal Detect/Link Fault Clock/Data RecoverySdasela TRGCLKA±Power Control ReclockerReclocker Serial Output Drivers Output BusDevice Configuration and Control Interface Device Reset StateLatch Types Static Latch ValuesDisables all output drivers Transmit Bist function is enabledReset sampled LOW disables all output drivers Phase Alignment Buffer Document # 38-02100 Rev. *BJtag ID Jtag SupportBISTSTA, RXDA0, RXDA1 Bisterror Biststart BISTSTA, RXDA0, RXDA1 = BistwaitBistdatacompare 000 BistlastbadMaximum Ratings CYV15G0104TRB DC Electrical CharacteristicsOperating Range CYV15G0104TRB AC Electrical Characteristics AC Test Loads and WaveformsParameter Description Min Max Unit Txrateb = 0, Txckselb =Txrateb = 1, Txckselb = TXRATEB= 0, Txckselb =PLL Characteristics CYV15G0104TRB Reclocker Output PLL CharacteristicsCYV15G0104TRB HOTLink II Transmitter Switching Waveforms CapacitanceParameter Description Test Conditions Max Unit Transmit Interface Write Timing Txclkb selectedTxrateb = Txrate =Rxratea = Bus Configuration Write Timing VCC Power Reset Lvttl in PUNo Connect GND GroundTXDB2 Lvttl TXDB9 LvttlRXCLKA+ Lvttl OUT Repdoa Lvttl OUTPackage Diagram Ordering InformationSpeed Ordering Code Package Type Operating Name RangeREV ECN no Issue ORIG. Description of Change Date Document HistoryFRE SUA

BIST_START (101)

{BISTSTA, RXDA[0], RXDA[1]} =

BIST_WAIT (111)

BIST_DATA_COMPARE (000, 001)

BIST_LAST_BAD (100)

BIST_LAST_GOOD (010)

BIST_ERROR (110)

Figure 2. Receive BIST State Machine