Cypress CYV15G0104TRB Reclocking Deserializer Path Block Diagram, Serializer Path Block Diagram

					CYV15G0104TRB
Reclocking Deserializer Path Block Diagram							RESET
					JTAG		TRST
TRGRATEA							TMS
					Boundary
	x2						TCLK
TRGCLKA					Scan
							TDI
					Controller
							TDO
SDASEL[2..1]A[1:0]
LDTDEN
	Receive						LFIA
INSELA	Signal		BISTLFSR		Output Register
	Monitor	Shifter				10
INA2+				10			RXDA[9:0]
	Data
INA1+			10
INA1–	Clock &						BISTSTA
INA2–	Recovery				⎟2
ULCA	PLL						RXCLKA+
							RXCLKA–
SPDSELA		RXBISTA[1:0]
RXPLLPDA
			RXRATEA
	Recovered Character Clock	Recovered Serial Data				ROE[2..1]A
					Register
	Clock Multiplier
	Reclocker		ROE[2..1]A				ROUTA1+
	Output PLL						ROUTA1–
							ROUTA2+
RECLKOA							ROUTA2–
	Character-Rate Clock
REPDOA
				Bit-Rate Clock
Serializer Path Block Diagram			Bit-Rate Clock				= Internal Signal

REFCLKB+

REFCLKB–

TXRATEB

SPDSELB

Transmit PLL	TOE[2..1]B
Clock Multiplier

TXCLKOB

TXERRB

TXCLKB

	TXCKSELB
TXDB[9:0]	10

0	1
Input Register

Character-Rate Clock
PABRSTB			TXBISTB			TOE[2..1]B
						TOUTB1+
10		10		10		TOUTB1–
PhaseAlign-	Buffer		BISTLFSR		Shifter	TOUTB2+
						TOUTB2–

Device Configuration and Control Block Diagram		= Internal Signal
		RXRATEA
		RXPLLPDA
WREN		TRGRATEA
	Device Configuration	TXRATEB
ADDR[2:0]		TXCKSELB
	and Control Interface
		PABRSTB
DATA[6:0]
		SDASEL[2..1]A[1:0]
		TOE[2..1]B
		ROE[2..1]A
		RXBISTA[1:0]
		TXBISTB
Document #: 38-02100 Rev. *B		Page 3 of 27

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