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Eurotech Appliances PXA255 General purpose I/O, Data bus, PXA255 data, VIPER inputs, Most Significant Byte

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VIPER Technical Manual	Detailed hardware description

General purpose I/O

Eight general-purpose input lines and eight general-purpose output lines are provided on connector PL9.

To read from IN[0:7], read the least significant byte located at offset 0x500000 from CS5 (0x14000000) to sample the 8 inputs from PL9.

VIPER inputs	PXA255 data
IN0	D0			3.3V
IN1	D1			10k
IN1	D1	PXA255	D[0:7]	Transceiver IN[0:7] ohms PL9
IN2	D2

IN3D3

IN4D4

IN5D5

IN6D6

IN7D7

The PXA255 is not designed to interface to 8-bit peripherals, so when the 8-bits of data are read only the least significant byte from the word contains the data.

Data bus

Most Significant Byte

Least Significant Byte

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Don’t Care	IN Data

Contents

VIPER / VIPER-Lite Technical Manual VIPER Technical Manual Contents Getting started Detailed hardware description VIPER address map Translations made by the MMU Introduction VIPER ‘at a glance’ VIPER-Lite‘at a glance’ VIPER features Network support Trusted Platform Module (TPM) [optional] Real time clock (RTC) Watchdog General purpose I/O (GPIO) VIPER support products •CYCLOPS •VIPER-ICE(Industrial Compact Enclosure) development kits Development kits available for the VIPER Windows CE/CE 5.0 development kit Embedded Linux development kit Wind River VxWorks 5.5 development kit Entry level development kits for VIPER or VIPER-Lite Windows CE / CE 5.0 development kit •Embedded Linux development kit Product handling and environmental compliance Conventions Tables Byte lane Getting started Using the VIPER Using the audio features Using the USB host Using the USB client Using the Ethernet interface Using the PC/104 expansion bus Detailed hardware description VIPER block diagram VIPER address map Translations made by the MMU PXA255 processor PXA255 GPIO pin assignments Page Page NoAF Signal name Active Sleep Function See section… Real time clock Watchdog timer Memory Static RAM Least Significant Byte CompactFLASH Region name Interrupt configuration and reset register [ICR] ICR Bit Functions Name Interrupt assignments PC/104 interrupt register [PC104I1] PC/104 interrupt register [PC104I2] (not available under Windows CE) Value Function PC/104 interrupts under embedded Linux and VxWorks PC/104 interrupts under Windows CE Flat panel display support TFT panel data bit mapping to the VIPER Panel data bus bit 18-bitTFT 12-bitTFT 9-bitTFT STN panel data bit mapping to the VIPER Dual scan colour STN Dual scan mono STN VIPER Active display signal (TFT) LCD backlight enable LCD logic supply enable LCD backlight brightness control STN BIAS voltage VIPER-FPIF1details Connector Function VIPER-FPIF1connectors LK1 – TFT clock delay selection PL1 – VIPER LCD cable connector Pin PL2 – Generic LCD connector PL3 – Direct connection to a NEC NL3224BC35-205.5inch 320x240 TFT display PL4 – Backlight inverter connector Pin Signal name PL5 – STN Bias connector FPIF-LVDS-TXdetails Connector FPIF-LVDS-TXconnectors JP1 – TX strobe selection JP2 – Cable power selection JP3 – MSL selection J1 – VIPER LCD cable connector J2 – LVDS Hirose connector J3 – LVDS MDR connector FPIF-LVDS-RXdetails FPIF-LVDS-RXconnectors JP1 – LCD power selection JP2 – Backlight power selection Page Page As viewed from the connector pins FPIF-CRTdetails FPIF-CRTconnectors J2 – CRT connector Audio General purpose I/O VIPER outputs PXA255 GPIO Register Address VIPER-I/O USB host interface USB client interface 10/100BaseTX Ethernet Ethernet signal mapping between VIPER and Ethernet breakout connectors Ethernet breakout PL3 RJ45 Ethernet LED signal mapping between VIPER and Ethernet breakout connectors Ethernet breakout PL2 – Serial COMs ports COM4 – RS232 interface COM5 – RS422/485 interface RS422 RS485 Typical RS422 and RS485 connection PC/104 interface VIPER PC/104 interface details PC/104 8-bitI/O read/write access cycles PC/104 16-bitI/O read/write access cycles PC/104 8-bitmemory write access cycle PC/104 16-bitmemory read/write access cycles Unsupported PC/104 interface features TPM JTAG and debug access Power and power management Power supplies Power management Processor current estimations Current saving from 5V when processor core is in performance mode Vcore (V) Asleep Current saving from 5V when processor core is in power saving mode Power savings Power saving mode Performance mode CPU Audio External peripheral device power estimations Device Part number Condition Power estimate examples Example 2: VIPER [Linux] at 200MHz in performance mode + LCD with backlight on Page Processor power management DAC Data Hex value CPU core voltage Comment LTC1659 DAC pin function Interrupt configuration and reset register ICR bit functions UART power management GPIO12 Operation status Transmitters Receivers Audio power management TPM Wake up events SourceGPIO Connectors, LEDs and jumpers Connectors PL1 – 10/100BaseTX Ethernet connector PL2 – Ethernet status LEDs connector As viewed from the connector pins COM5 COM3 COM2 COM4 COM1 PL5 – CompactFLASH connector PL6 – Audio connector PL7 – USB connector PL8 – TPM Tamper detect connector (optional) PL9 – GPIO connector PL10 – JTAG connector PL11 & PL12 – PC/104 connectors PL12 PL11 Row D Row C PL16 – Power connector PL17 – USB client connector 2011-1x2GSB/SN Status LEDs Jumpers RS485/422 configuration – LK4, LK5, LK6 and LK7 on JP1 LK4 Description LK5 Description LK6 & LK7 Description LCD supply voltage – LK8 on JP2 LK8 Description Battery jumper – LK9 on JP4 LK9 Description Appendix A – Contacting Eurotech Eurotech sales Eurotech technical support Eurotech Group Appendix B – Specification Appendix C – Mechanical diagram Appendix D – Reference information National Semiconductor Corporation Koninklijke Philips Electronics N.V Maxim Integrated Products Inc Linear Technology Corporation Appendix E – Acronyms and abbreviations Page Appendix F – RoHS-6Compliance - Materials Declaration Form Confirmation of Environmental Compatibility for Supplied Products Index