VIPER Technical Manual | Power and power management |
|
|
The power manager in the PXA255 offers the ability to disable the clocks to the different internal peripherals. By default, all clocks are enabled after reset. To reduce power consumption disable the clocks for any unused peripherals.
The clock speed of the processor core, PXbus (the internal bus connecting the microprocessor core and the other blocks of the PXA255), LCD and SDRAM can also be changed to achieve a balance between performance and power consumption. For more details on the internal power manager please see the PXA255 Developer’s Manual on the Development Kit CD.
To adjust the core voltage, write the values shown in the following table to the LTC1659 DAC. When changing the core voltage it is important to ensure that the internal CPU clock is set to the correct voltage range. The CPU core supply must be set to a defined range for a particular clock. Please refer to the LTC1659 datasheet, Clocks and Power Manager section in the PXA255 Applications Processors Developer's Manual and Power Consumption Specifications section in the PXA255 Processor Electrical, Mechanical and Thermal Specification on the Development Kit CD.
| DAC Data Hex value | CPU core voltage | Comment | |
0x000 | 1.65V | Not recommended to set the VCORE above | |
|
| 1.3V as the power consumption will increase | |
|
| for no performance benefit. | |
0x325 | 1.29V | Typical VCORE for peak voltage range at | |
|
| 400MHz operation. | |
|
| Maximum VCORE for medium voltage range | |
|
| at 200MHz operation. | |
0xDE5 | 1.1V | Typical VCORE for high voltage range at | |
|
| 300MHz operation. | |
0xFFF | 1.06V | Typical VCORE for low voltage and medium | |
|
| voltage range, suitable for 100MHz to 200MHz | |
|
| operation. | |
|
|
|
|
|
|
|
|
When the microprocessor is in sleep mode, the CPU core voltage is shutdown.
When changing between CPU core voltages it is important to adjust the DAC Data in steps of no greater than 0x100 at a time.
© 2007 Eurotech Ltd Issue E | 81 |