
VIPER Technical Manual | Detailed hardware description |
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The PC/104 bus signals are compatible with the ISA bus electrical timing definitions.
For details of PC/104 Interrupts please see PC/104374Hinterrupts, page 3075H.
All signals (except interrupts) between the PXA255 and the PC/104 are buffered. The interrupts are connected and processed by CPLD. When the PC/104 bus is not in use all output signals, with the exception of the clock signals, are set to their inactive state.
The VIPER provides +5V to a PC/104
The following diagrams show the activity of the VIPER PC/104 interface for 8 and 16- bit I/O and memory space accesses.
PC/104AEN
BALE
SBHE
A<0:15>
IOCS16
IOCHRDY
IOR/IOW
DATA (read)
DATA (write)
VALID | VALID |
VALID | VALID |
VALID | VALID |
© 2007 Eurotech Ltd Issue E | 68 |