![Manual background](/images/new-backgrounds/54107/5410721x1.webp)
| Prelminary |
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| MB91401 | |
2004.11.12 |
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| ETHERNET MAC CONTROLLER (17 pin) |
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| Pin name | Pin no. | Polarity | I/O | Circuit | Function/application |
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| Clock input for reception pin |
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| RXCLK | 48 | IN | D | MII sync signal during reception. The frequency is 2.5 MHz |
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| at 10 Mbps and 25 MHz at 100 Mbps. |
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| Posi- |
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| Receive error input pin |
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| RXER | 113 | IN | D | It is recognized that there is an error in the reception packet |
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| tive |
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| when “1” is input from the PHY device at receiving. |
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| RXDV | 172 | Posi- | IN | D | Receive data valid input pin |
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| tive | It is recognized that receive data is effective. |
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| Posi- |
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| Career sense input pin |
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| RXCRS | 115 | IN | D | The state that the reception or the transmission is done is |
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| tive |
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| recognized. |
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| RXD3 | 114 |
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| RXD2 | 47 | | IN | D | Receive data input pins |
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| RXD1 | 112 |
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| RXD0 | 45 |
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| Collision detection input pin |
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| COL | 173 | Posi- | IN | D | When TXEN signal is active and “1”, the collision is |
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| tive | recognized. The collision is not recognized without these |
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| Clock input for transfer pin |
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| TXCLK | 46 | IN | D | It becomes synchronous of MII when transmitting. The |
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| frequency is 2.5 MHz at 10 Mbps and 25 MHz at 100 Mbps. |
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| Transfer enable output pin |
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| TXEN | 43 | OUT | F | It is shown that effective data is on the TXD bus. It is output |
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| tive |
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| synchronizing with TXCLK. |
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| TXD3 | 171 |
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| Transfer data output pins |
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| TXD2 | 170 | |
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| OUT | F |
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| TXD1 | 111 |
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| synchronizing with TXCLK. |
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| TXD0 | 44 |
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| SMI clock output pin |
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| MDCLK | 222 | OUT | F | SMI IF clock pin |
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| Connect to SMI clock input pin of PHY device. |
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| MDIO | 224 | | I/O | B | SMI data input/output pin |
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| Connect to SMI data of PHY device. |
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