Fujitsu MB91401 manual Prelminary, 2004.11.12, Address, Register, Block

MB91401								Prelminary
								2004.11.12
	(Continued)
	Address			Register				Block
		+ 0	+ 1		+ 2		+ 3
	0000_067CH			
	0000_0680H	CSER [R/W]	CHER [R/W]				TCR [R/W]
		00000001	XXXXXXX1				00000000*1	Memory IF
	0000_0684H	RCR				
		00XXXXXX	00XXXXXX
	0000_0688H			
	to							Reserved
	0000_0FFCH

*1 : An initial value is a different register at the reset level. The display is the one at the INIT level.

*2 : An initial value is a different register at the reset level. The display is due to the INIT level by INITX.

*3 : An initial value is set by the WTH bit of the mode vector.

Address			Register				Block
	+ 0		+ 1		+ 2	+ 3
0000_1000H			DMASA0		[R/W]
		XXXXXXXX XXXXXXXX			XXXXXXXX XXXXXXXX
0000_1004H			DMADA0		[R/W]
		XXXXXXXX XXXXXXXX			XXXXXXXX XXXXXXXX
0000_1008H			DMASA1		[R/W]
		XXXXXXXX XXXXXXXX			XXXXXXXX XXXXXXXX
0000_100CH			DMADA1		[R/W]
		XXXXXXXX XXXXXXXX			XXXXXXXX XXXXXXXX
0000_1010H			DMASA2		[R/W]
		XXXXXXXX XXXXXXXX			XXXXXXXX XXXXXXXX
							DMAC
0000_1014H			DMADA2		[R/W]
		XXXXXXXX XXXXXXXX			XXXXXXXX XXXXXXXX
0000_1018H			DMASA3		[R/W]
		XXXXXXXX XXXXXXXX			XXXXXXXX XXXXXXXX
0000_101CH			DMADA3		[R/W]
		XXXXXXXX XXXXXXXX			XXXXXXXX XXXXXXXX
0000_1020H			DMASA4		[R/W]
		XXXXXXXX XXXXXXXX			XXXXXXXX XXXXXXXX
0000_1024H			DMADA4		[R/W]
		XXXXXXXX XXXXXXXX			XXXXXXXX XXXXXXXX
0000_1028H				
to							Reserved
0000_FFFCH

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