Fujitsu MB91401 Interrupt Address of TBR Interrupt source Offset, NMI Non Maskable Interrupt

MB91401						Prelminary
						2004.11.12
	(Continued)
		Interrupt number		Interrupt		Address of TBR
	Interrupt source				Offset		RN
		Decimal	Hexa-	level		default
			decimal
	System reserved	68	44		2ECH	000FFEECH	
	System reserved	69	45		2E8H	000FFEE8H	
	System reserved	70	46		2E4H	000FFEE4H	
	System reserved	71	47		2E0H	000FFEE0H	
	System reserved	72	48		2DCH	000FFEDCH	
	System reserved	73	49		2D8H	000FFED8H	
	System reserved	74	4A		2D4H	000FFED4H	
	System reserved	75	4B		2D0H	000FFED0H	
	System reserved	76	4C		2CCH	000FFECCH	
	System reserved	77	4D		2C8H	000FFEC8H	
	System reserved	78	4E		2C4H	000FFEC4H	
	System reserved	79	4F		2C0H	000FFEC0H	
		80	50		2BCH	000FFEBCH	
	Used by INT instruction	to	to		to	to
		255	FF		000H	000FFC00H

(2) NMI (Non Maskable Interrupt)

NMIs have the highest priority among the interrupt sources handled by this module.

An NMI is always selected whenever other types of interrupt sources occur at the same time.

•If an NMI occurs, the interrupt controller passes the information to the CPU : Interrupt level : 15 (01111B)

Interrupt number : 15 (0001111B)

•NMI detection

NMIs are set and detected by the external interrupt/NMI controller. This module only generates an interrupt level, interrupt number, and MHALTI upon NMI request.

•Suppressing DMA transfer upon NMI request

When an NMI request occurs, the MHALTI bit in the HRCL register is set to "1", suppressing DMA transfer. To permit DMA transfer, clear the MHALTI bit to "0" at the end of the NMI routine.

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