![Interrupt](/images/new-backgrounds/54107/5410791x1.webp)
MB91401 |
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| 2004.11.12 |
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| (Continued) |
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| Interrupt number | Interrupt |
| Address of TBR |
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| Interrupt source |
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| Offset | RN |
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| Decimal | Hexa- | level | default |
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| decimal |
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| System reserved | 68 | 44 | | 2ECH | 000FFEECH | |
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| System reserved | 69 | 45 | | 2E8H | 000FFEE8H | |
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| System reserved | 70 | 46 | | 2E4H | 000FFEE4H | |
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| System reserved | 71 | 47 | | 2E0H | 000FFEE0H | |
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| System reserved | 72 | 48 | | 2DCH | 000FFEDCH | |
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| System reserved | 73 | 49 | | 2D8H | 000FFED8H | |
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| System reserved | 74 | 4A | | 2D4H | 000FFED4H | |
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| System reserved | 75 | 4B | | 2D0H | 000FFED0H | |
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| System reserved | 76 | 4C | | 2CCH | 000FFECCH | |
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| System reserved | 77 | 4D | | 2C8H | 000FFEC8H | |
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| System reserved | 78 | 4E | | 2C4H | 000FFEC4H | |
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| System reserved | 79 | 4F | | 2C0H | 000FFEC0H | |
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| 80 | 50 | | 2BCH | 000FFEBCH | |
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| Used by INT instruction | to | to | to | to |
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| 255 | FF |
| 000H | 000FFC00H |
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(2) NMI (Non Maskable Interrupt)
NMIs have the highest priority among the interrupt sources handled by this module.
An NMI is always selected whenever other types of interrupt sources occur at the same time.
•If an NMI occurs, the interrupt controller passes the information to the CPU : Interrupt level : 15 (01111B)
Interrupt number : 15 (0001111B)
•NMI detection
NMIs are set and detected by the external interrupt/NMI controller. This module only generates an interrupt level, interrupt number, and MHALTI upon NMI request.
•Suppressing DMA transfer upon NMI request
When an NMI request occurs, the MHALTI bit in the HRCL register is set to "1", suppressing DMA transfer. To permit DMA transfer, clear the MHALTI bit to "0" at the end of the NMI routine.
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