Fujitsu MB91401 manual Interrupt Vector, Address of TBR, Interrupt source, Offset, Prelminary

MB91401						Prelminary
						2004.11.12
	■ INTERRUPT VECTOR
		Interrupt number		Interrupt		Address of TBR
	Interrupt source				Offset		RN
		Decimal	Hexa-	level		default
			decimal
	Reset	0	00		3FCH	000FFFFCH	
	Mode vector	1	01		3F8H	000FFFF8H	
	System reserved	2	02		3F4H	000FFFF4H	
	System reserved	3	03		3F0H	000FFFF0H	
	System reserved	4	04		3ECH	000FFFECH	
	System reserved	5	05		3E8H	000FFFE8H	
	System reserved	6	06		3E4H	000FFFE4H	
	Coprocessor absent trap	7	07		3E0H	000FFFE0H	
	Coprocessor error trap	8	08		3DCH	000FFFDCH	
	INTE instruction	9	09		3D8H	000FFFD8H	
	Instruction break exception	10	0A		3D4H	000FFFD4H	
	Operand break trap	11	0B		3D0H	000FFFD0H	
	Step trace trap	12	0C		3CCH	000FFFCCH	
	NMI request (tool)	13	0D		3C8H	000FFFC8H	
	Undefined instruction exception	14	0E		3C4H	000FFFC4H	
	NMI request	15	0F	FH fixed	3C0H	000FFFC0H	
	Ethernet MAC IF	16	10	ICR00	3BCH	000FFFBCH	4
	Authentication macro	17	11	ICR01	3B8H	000FFFB8H	5
	IPSec Accelerator/Code macro	18	12	ICR02	3B4H	000FFFB4H	8
	EX IF/GPIO	19	13	ICR03	3B0H	000FFFB0H	9
	USB/I2C/CARD IF	20	14	ICR04	3ACH	000FFFACH	
	External interrupt 5	21	15	ICR05	3A8H	000FFFA8H	
	External interrupt 6	22	16	ICR06	3A4H	000FFFA4H	
	External interrupt 7	23	17	ICR07	3A0H	000FFFA0H	
	Reload timer 0	24	18	ICR08	39CH	000FFF9CH	6
	Reload timer 1	25	19	ICR09	398H	000FFF98H	7
	Reload timer 2	26	1A	ICR10	394H	000FFF94H	
	UART0 (Reception completed)	27	1B	ICR11	390H	000FFF90H	0
	UART1 (Reception completed)	28	1C	ICR12	38CH	000FFF8CH	1
	UART0 (RX completed)	29	1D	ICR13	388H	000FFF88H	2
	UART1 (RX completed)	30	1E	ICR14	384H	000FFF84H	3
	DMAC0 (end error) Ethernet MAC IF	31	1F	ICR15	380H	000FFF80H	
	DMAC1 (end error) External IF	32	20	ICR16	37CH	000FFF7CH	
	DMAC2 (end error) USB	33	21	ICR17	378H	000FFF78H	

(Continued)

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