Fujitsu MB91401 manual Prelminary, 2004.11.12, Address, Register, Block

Prelminary	MB91401
2004.11.12

Address		Register				Block
	+ 0	+ 1		+ 2	+ 3
0000_0060H	SSR0 [R/W]	SIDR0 [R/W]		SCR0 [R/W]	SMR0 [R/W]	UART0
	00001-00	XXXXXXXX		00000100	00--0-0-
0000_0064H	UTIM0 [R]	(UTIMR0 [W])		DRCL0 [W]	UTIMC0 [R/W]	U-TIMER0
	00000000	00000000		--------	0--00001
0000_0068H	SSR1 [R/W]	SIDR1 [R/W]		SCR1 [R/W]	SMR1 [R/W]	UART1
	00001-00	XXXXXXXX		00000100	00--0-0-
0000_0048H	UTIM1 [R]	(UTIMR1 [W])		DRCL1 [W]	UTIMC1 [R/W]	U-TIMER1
	00000000	00000000		--------	0--00001
0000_0070H			
to						Reserved
0000_01FCH
0000_0200H		DMACA0		[R/W]
	00000000 00000000			0000XXXX XXXXXXXX
0000_0204H		DMACB0		[R/W]
	00000000 00000000		00000000 00000000
0000_0208H		DMACA1		[R/W]
	00000000 00000000			0000XXXX XXXXXXXX
0000_020CH		DMACB1		[R/W]
	00000000 00000000		00000000 00000000
0000_0210H		DMACA2		[R/W]
	00000000 00000000			0000XXXX XXXXXXXX
						DMAC
0000_0214H		DMACB2		[R/W]
	00000000 00000000		00000000 00000000
0000_0218H		DMACA3		[R/W]
	00000000 00000000			0000XXXX XXXXXXXX
0000_021CH		DMACB3		[R/W]
	00000000 00000000		00000000 00000000
0000_0220H		DMACA4		[R/W]
	00000000 00000000			0000XXXX XXXXXXXX
0000_0224H		DMACB4		[R/W]
	00000000 00000000		00000000 00000000
0000_0228H			
to						Reserved
0000_023CH
0000_0240H		DMACR		[R/W]		DMAC
	0XX00000 XXXXXXXX			XXXXXXXX XXXXXXXX
0000_0244H			
to						Reserved
0000_0300H
0000_0304H					ISIZE [R/W]	Instruction
					------10	Cache

(Continued)

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