Fujitsu MB91401 manual Pin name, Pin no, Function/application, Prelminary, 2004.11.12

Prelminary	MB91401
2004.11.12

SYSTEM (9 pin)

Pin name	Pin no.	Polarity	I/O	Circuit		Function/application
						Clock input pin
XINI	8		IN	D		Input pin of clock generated in clock generator. 10 MHz to
						50 MHz frequency can be input.
						Reset input pin
		Nega-				This pin inputs a signal to initialize the LSI.
INITXI	204		IN	D		When turning on the power supply, apply “0” to the pin until
		tive				the clock signal input to the CLKIN pin becomes stable.
						All built-in registers and external pins are initialized, and the
						built-in PLL is stopped when “0” is asserted to INITXI.
NMIX	206	Nega-	IN	D		NMI input pin
		tive				Non-Maskable Interrupt signal
INT7	150					External interrupt input pins
						These pins input an external interrupt request signal.
INT6	87		IN	D
						For external interrupt detection, set the ENIR, EIRR and
INT5	16
						ELVR registers of the FR core.
MDI2	80					Mode pins
MDI1	142		IN	D		These pins determine the operation mode of the LSI.
MDI0	79					Always set this bit to “001”.
OSCILLATOR (3 pin)
Pin name	Pin no.	Polarity	I/O	Circuit		Function/application
OSCEA	12		IN	G		Crystal oscillation input pin
						Input pin of crystal oscillation cell.
		Nega-				Crystal oscillation control input pin
OSCC	145		IN	D		Oscillation control pin of crystal oscillation cell.
		tive				“0” : Oscillation
						“1” : Oscillation stop
OSCEB	10		OUT	G		Crystal oscillation output pin
						Output pin of crystal oscillation cell.
PLL CONTROL (5 pin)
Pin name	Pin no.	Polarity	I/O	Circuit		Function/application
						PLL/through mode (reset) switching input pin
PLLS	147		IN	D	“0” : PLL through mode (oscillation stop)
						“1” : PLL oscillation mode
						Input clock division ratio select input pin
PLLSET1	144		IN	D		“0” : Input clock direct
						“1” : Input clock divided by 2
						Division ratio select input to PLL FB pin
PLLSET0	81		IN	D	“0” : Two dividing frequency is input to the terminal FB.
						“1” : Four dividing frequency is input to the terminal FB.
						PLL bypass select input pin
PLLBYPAS	9		IN	D		“0” : PLL used
						“1” : PLL unused
						Input clock switching input pin
CLKSEL	77		IN	D		“0” : XINI (External clock)
						“1” : Built-in OSC generating clock

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