Fujitsu MB91401 manual I/O Map, Address, Register, Block, Prelminary, 2004.11.12

MB91401	Prelminary
	2004.11.12

■I/O MAP

This shows the location of the various peripheral resource registers in the memory space.

[How to read the table]

Address		Register				Block
	+ 0	+ 1	+ 2		+ 3
0000_0000H		
						Reserved
0000_003CH
0000_0040H	EIRR [R/W]	ENIR [R/W]		ELVR [R/W]		Ext Int
	00000000	00000000	00000000 00000000

Read/Write attribute Initial value after a reset

Register name (First-column register at address 4n; second-column register at address 4n + 2)

Left most register address (When accessing it by word, the register of column 1 is positioned on the MSB side of data.)

Note : Initial values of register bits are represented as follows :

“1”	: Initial Value		“1”
“0”	: Initial Value		“0”
“X”	: Initial Value		“X”
“-”	: Access prohibited in reserved area.
Address					Register			Block
			+ 0		+ 1	+ 2	+ 3
0000_0000H					
	to							Reserved
0000_003CH
0000_0040H		EIRR [R/W]			ENIR [R/W]	ELVR	[R/W]	Ext Int
		00000000			00000000	00000000	00000000
0000_0044H		DICR [R/W]			HRCL [R/W]			DLYI/I-unit
			-------0		0-11111
0000_0048H			TMRLR0 [W]			TMR0	[R]
			XXXXXXXX XXXXXXXX			XXXXXXXX XXXXXXXX
								Reload Timer 0
0000_004CH						TMCSR0 [R/W]
						----0000	00000000
0000_0050H			TMRLR1 [W]			TMR1 [R]
			XXXXXXXX XXXXXXXX			XXXXXXXX XXXXXXXX
								Reload Timer 1
0000_0054H						TMCSR1 [R/W]
						----0000	00000000
0000_0058H			TMRLR2 [W]			TMR2 [R]
			XXXXXXXX XXXXXXXX			XXXXXXXX XXXXXXXX
								Reload Timer 2
0000_005CH						TMCSR2 [R/W]
						----0000	00000000

(Continued)

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