Gateway 9315 POST code checkpoints, Check, point, Description, Diagnostic LED decoder

POST code checkpoints

The following table shows the checkpoints, LED codes, and task description of events that may occur during the POST portion of the BIOS:

Check	Diagnostic LED decoder				Description
point	G=Green, R=Red, O=Orange
03	Off	Off	G	G	Disable NMI, Parity, video for EGA, and DMA controllers. Initialize
					BIOS, POST, Runtime data area. Also initialize BIOS modules
					on POST entry and GPNV area. Initialized CMOS as mentioned
					in the Kernel Variable “wCMOSFlags.”
04	Off	G	Off	Off	Check CMOS diagnostic byte to determine if battery power is OK
					and CMOS checksum is OK. Verify CMOS checksum manually
					by reading storage area. If the CMOS checksum is bad, update
					CMOS with power-on default values and clear passwords.
					Initialize status register A.
					Initialize data variables that are based on CMOS setup
					questions. Initializes both the 8259 compatible PICs in the
					system.
05	Off	G	Off	G	Initialize the interrupt controller in hardware (generally PIC) and
					interrupt vector table.
06	Off	G	G	Off	Do R/W test to CH-2 count reg. Initialize CH-0 as system timer.
					Install the POSTINT1Ch handler. Enable IRQ-0 in PIC for system
					timer interrupt.
					Traps INT1Ch vector to “POSTINT1ChHandlerBlock.”
08	G	Off	Off	Off	Initialize the CPU. The BAT test is being done on KBC. Program
					the keyboard controller command byte is being done after Auto
					detection of KB/MS using AMI KB-5.
C0	R	R	Off	Off	Early CPU Init Start — Disable Cache - Init Local APIC
C1	R	R	Off	G	Set up boot strap processor information.
C2	R	R	G	Off	Set up boot strap processor for POST.
C5	R	O	Off	G	Enumerate and set up application processors.
C6	R	O	G	Off	Re-enable cache for boot strap processor.
C7	R	O	G	G	Early CPU Init Exit.
0A	G	Off	G	Off	Initialize the 8042 compatible keyboard controller.
0B	G	Off	G	G	Detect the presence of PS/2 mouse.
0C	G	G	Off	Off	Detect the presence of keyboard in KBC port.

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