Check

Diagnostic LED decoder

Description

point

G=Green, R=Red, O=Orange

 

 

 

 

 

 

 

D6

R

O

G

R

Both key sequence and OEM-specific method is checked to

 

 

 

 

 

determine if BIOS recovery is forced. Main BIOS checksum is

 

 

 

 

 

tested. If BIOS recovery is necessary, control flows to checkpoint

 

 

 

 

 

E0. See Bootblock Recovery Code Checkpoints section of

 

 

 

 

 

document for more information.

 

 

 

 

 

 

D7

R

O

G

O

Restore CPUID value back into register. The Bootblock-Runtime

 

 

 

 

 

interface module is moved to system memory and control is given

 

 

 

 

 

to it. Determine whether to execute serial flash.

 

 

 

 

 

 

D8

O

R

Off

R

The Runtime module is uncompressed into memory. CPUID

 

 

 

 

 

information is stored in memory.

 

 

 

 

 

 

D9

O

R

Off

O

Store the Uncompressed pointer for future use in PMM. Copying

 

 

 

 

 

Main BIOS into memory. Leaves all RAM below 1 MB

 

 

 

 

 

Read-Write, including E000 and F000 shadow areas, but closing

 

 

 

 

 

SMRAM.

 

 

 

 

 

 

DA

O

R

G

R

Restore CPUID value back into register. Give control to BIOS

 

 

 

 

 

POST (ExecutePOSTKernel).See “POST code checkpoints” on

 

 

 

 

 

page 111 for more information.

 

 

 

 

 

 

E1-E8

-

-

-

-

OEM memory detection/configuration error. This range is

EC-EE

reserved for chipset vendors and system manufacturers. The

error associated with this value may be different from one

 

 

platform to the next.

 

 

Bootblock recovery code checkpoints

The bootblock recovery code gets control when the BIOS determines that a BIOS recovery needs to occur because the user has forced the update or the BIOS checksum is corrupt. The following table provides the diagnostic LED codes for these checkpoints and describes the type of checkpoints that may occur during the Bootblock recovery portion of the BIOS:

Check

Diagnostic LED decoder

Description

point

G=Green, R=Red, O=Orange

 

 

 

 

 

 

 

E0

R

R

R

Off

Initialize the floppy controller in the super I/O. Some interrupt

 

 

 

 

 

vectors are initialized. DMA controller is initialized. 8259 interrupt

 

 

 

 

 

controller is initialized. L1 cache is enabled.

 

 

 

 

 

 

E9

O

R

R

G

Set up floppy controller and data. Attempt to read from floppy.

 

 

 

 

 

 

EA

O

R

O

Off

Enable ATAPI hardware. Attempt to read from ARMD and ATAPI

 

 

 

 

 

CDROM.

 

 

 

 

 

 

EB

O

R

O

G

Disable ATAPI hardware. Jump back to checkpoint E9.

 

 

 

 

 

 

www.gateway.com

115