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LED Name

Function

Location

Color

Description

 

 

 

 

 

 

 

NIC status LEDs

Identify NIC states

Front panel and

Green/

 

 

 

 

 

 

 

 

back I/O panel

Yellow

 

 

 

 

 

RJ-45 connectors

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LED 1 Green (On) - NIC linked

 

 

 

 

LED 1 Green (Blinking) - NIC

 

 

 

 

activity

 

 

 

 

LED 1 (Off) - No link

 

 

 

 

LED 2 Yellow (On) Link speed 1

 

 

 

 

Gbps

 

 

 

 

LED 2 Yellow (Off) - Link at other

 

 

 

 

speed

 

 

 

 

 

Power LED

Identify the power

Front panel

Blue

Off - Power is off (or S5)

 

state of the system

 

 

On - Power is on (or S0)

 

 

 

 

 

Power supply

Identify power

Power supply

Green or Red

Green (On) - Power supply good

status LED

supply fault

module

 

and receiving power

 

 

 

 

Red (On) - Power supply fault

 

 

 

 

Off-Powersupplynotreceiving

 

 

 

 

power

 

 

 

 

 

Diagnostic LEDs

The BIOS sends a 1-byte hex code to port 80 prior to each POST task. These codes are displayed on eight orange LEDs, located on the system board and available at the back of the server chassis. They can provide troubleshooting information in the event of a system hang during POST.

POST code checkpoints

The following table shows the checkpoints, LED codes, and task description of events that may occur during the POST portion of the BIOS:

Check Description point

03Disable NMI, Parity, video for EGA, and DMA controllers. Initialize BIOS, POST, Runtime data area. Also initialize BIOS modules on POST entry and GPNV area. Initialized CMOS as mentioned in the Kernel Variable “wCMOSFlags.”

04Check CMOS diagnostic byte to determine if battery power is OK and CMOS checksum is OK. Verify CMOS checksum manually by reading storage area. If the CMOS checksum is bad, update CMOS with power-on default values and clear passwords. Initialize status register A.

Initialize data variables that are based on CMOS setup questions. Initialize both the 8259 compatible PICs in the system.

05Initialize the interrupt controller in hardware (generally PIC) and interrupt vector table.

06Do R/W test to CH-2 count reg. Initialize CH-0 as system timer. Install the POSTINT1Ch handler. Enable IRQ-0 in PIC for system timer interrupt. Trap INT1Ch vector to “POSTINT1ChHandlerBlock.”

08Initialize the CPU. The BAT test is being done on KBC. The keyboard controller command byte is being programmed after Auto detection of KB/MS using AMI KB-5.

C0 Early CPU Init Start — Disable Cache - Init Local APIC

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