
Analog Troubleshooting
Phase Lock Loops Principles of Operation
General Description
The fundamental RF signal input to the A6 RF Module (2 to 6.2 GHz) is generated by the AllA YTO
All phase lock loops are referenced, either directly or indirectly, to the A22 10 MHz Standard. Figure 1. shows the relationship between the various loops as well as defining the assemblies associated with the loops.
2 0 M H z
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3 . 3 GHz |
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t |
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H E T E R O D Y N E |
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| fYTO | |
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1 0 0 M H z |
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R E F E R E N C E |
| 1 0 M H z a n d 1 0 0 | M H z | PLLl & PLL3 |
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L O O P |
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(A7Al.A7AZ) |
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1 0 M H z |
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1 0 M H z |
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| 1 0 | M H z | P L L 2 |
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S T A N D A R D |
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(A2’J) |
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Figure 1. Phase Lock Loops (Synthesizer), Block Diagram
Analog Troubleshooting 1