HP XA manual PAC Chip 440LX, PL Bus Interface, PCI Bus Interface, System Board Chip-Set

2 System Board

Chip-Set

Chip-Set

The Intel AGPset is comprised of two chips. The 440LX PAC chip and the

PIIX4chip.

•The PAC chip (440LX) is the bridge between four buses: the PL (GTL) bus, the main memory bus, the PCI bus and the AGP (graphic) bus.

•The PIIX4 chip is the bridge between three buses: the PCI bus, the SM bus and the ISA bus. In addition, it contains the IDE controller, USB controller and Power Management logic

	The PAC Chip (440LX)
	The PAC chip, called the Intel 440LX AGPset, is contained in a Ball Grid
	Array (BGA) package, giving a smaller footprint and higher reliability.
	The PAC chip integrates a Host-to-PCI bridge, optimized DRAM controller
	and data path, and an Accelerated Graphics Port (AGP) interface. The AGP
	is a high performance, component level interconnect, targeted at 3D
	graphics applications.
PL Bus Interface	The PAC chip monitors each cycle that is initiated by the processor, and
	forwards those to the PCI bus that are not targeted at the local memory. It
	translates PL bus cycles into PCI bus cycles.
	The chip can support one or two Pentium II processors, at up to 66 MHz FSB
	clock frequency. Refer to page 35 for a description of the devices on the
	Processor-Local Bus.
PCI Bus Interface	The PCI bus interface is PCI 2.1 compliant.
	Sequential PL-to-PCI memory write cycles are translated into PCI zero wait
	state burst cycles. The maximum PCI burst transfer can be between
	256 bytes and 4 KB. The chip supports advanced snooping for PCI master
	bursting, and provides a pre-fetch mechanism dedicated for IDE read.
	The PCI arbiter supports PCI bus arbitration for up to six masters using a
	rotating priority mechanism. Its hidden arbitration scheme minimizes
	arbitration overhead. Additional logic on the PC Workstation extends the
	number of fully supported masters to seven (440LX master not counted).
	Refer to page 39 for a description of the devices on the Processor-Local Bus.

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