2 System Board

Chip-Set

PCI Bus Interface

This part of the chip is responsible for transferring data between the PCI bus

 

and the ISA expansion bus. It performs PCI-to-ISA, and ISA-to-PCI bus cycle

 

translation. It supports the Plug-and-Play mechanism. Data buffers are

 

provided, to isolate the PCI and ISA buses. Refer to page 39 for a description

 

of the devices on the PCI Bus.

ISA Bus Interface

As well as accepting cycles from the PCI bus interface, and translating them

 

for the ISA bus, the ISA bus interface also requests the PCI master bridge to

 

generate PCI cycles on behalf of a DMA or ISA master. The ISA bus interface

 

contains a standard ISA bus controller and data buffering logic. It can

 

directly support six ISA slots without external data or address buffering.

 

Refer to page 45 for a description of the devices on the ISABus.

SMBus Controller

The System Management (SM) bus is a two-wire serial bus provided by the

 

PIIX4 controller. It runs at a maximum of 16 kHz. The bus monitors some of

 

the hardware functions of the main board, both during boot-up and run-time.

 

All accesses to the SM bus are handled by the main processor, via the PIIX4

 

SM bus registers. Refer to page 43 for a description of the devices on the SM

 

(System Management) Bus.

IDE Controller

The PCI master/slave IDE controller, supporting four devices, two on each of

 

two channels, is described on page 39.

USB Controller

The PCI USB (Universal Serial Bus) controller, supports two stacked USB

 

connectors on the back panel. These ports are built into the PIIX4

 

controller, as standard USB ports. The USB is described in detail on page 40.

Ultra DMA Controller

The seven channel DMA controller incorporates the functionality of two

 

82C37 DMA controllers. Channels 0 to 3 are for 8-bit DMA devices, while

 

channels 5 to 7 are for 16-bit devices (see page 82). The channels can be

 

programmed for any of the four transfer modes: the three active modes

 

(single, demand, block), can perform three different types of transfer: read,

 

write and verify. The address generation circuitry supports a 24-bit address

 

for DMA devices.

Interrupt Controller

The interrupt controller incorporates the functionality of two 82C59

 

interrupt controllers. The two controllers are cascaded, supporting 15

 

interrupts (edge/level triggered). A table on page 83 shows how the master

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Image 33
HP XA ISA Bus Interface, SMBus Controller, IDE Controller, USB Controller, Ultra DMA Controller, Interrupt Controller