5 Power-On Self-Test and Error Messages

Order in Which the Tests are Performed

The following table lists the POST checkpoint codes written at the start of each test.

Checkpoint

POST Routine Description

 

Code

 

 

 

 

 

 

02h

Verify Real Mode

 

 

 

 

03h

Disable Non-Maskable Interrupt (NMI)

 

 

 

 

04h

Get CPU type

 

 

 

 

06h

Initialize system hardware

 

 

 

 

08h

Initialize chipset with initial POST values

 

 

 

 

09h

Set IN POST flag

 

 

 

 

0Ah

Initialize CPU registers

 

 

 

 

0Bh

Enable CPU cache

 

 

 

 

0Ch

Initialize caches to initial POST values

 

 

 

 

0Eh

Initialize I/O component

 

 

 

 

0Fh

Initialize the local bus IDE

 

 

 

 

10h

Initialize Power Management

 

 

 

 

11h

Load alternate registers with initial POST values

 

 

 

 

12h

Restore CPU control word during warm boot

 

 

 

 

13h

Initialize PCI Bus Mastering devices

 

 

 

 

14h

Initialize keyboard controller

 

 

 

 

17h

Initialize cache before memory autosize

 

 

 

 

18h

8254 timer initialization

 

 

 

 

1Ah

8237 DMA controller initialization

 

 

 

 

1Ch

Reset Programmable Interrupt Controller

 

 

 

 

24h

Set ES segment register to 4 GB

 

 

 

 

26h

Enable A20 line

 

 

 

 

28h

Autosize DRAM

 

 

 

 

29h

Initialize POST Memory Manager

 

 

 

 

 

 

 

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