HP XA Intel Pentium II Microprocessor, “split, -transaction”, Devices on the Processor-LocalBus, •Dynamic execution to speed up software performance

2 System Board

Devices on the Processor-Local Bus

Devices on the Processor-Local Bus

The Processor-Local (PL) bus of the Pentium II processors, also referred to as their FSB (Front Side Bus), is implemented in the GTL+ technology. This technology features open-drain signal drivers that are pulled-up to 1.5 V through 56 ohm resistors on both ends of the bus; these resistors also act as bus terminators, and are integrated in the Pentium II processors.

The supported operating frequencies of the GTL+ bus are 60 MHz and

66 MHz. The width of the data bus is 64 bits, the width of the address is 32 bits.

The control signals of the PL bus allows the implementation of a “split - transaction” bus protocol. This allows the Pentium II processor to send its request (such as asking for the contents of a given memory address) and then to release the bus, rather than waiting for the result, thereby allowing to accept another request. The 440LX as target device then requests the bus again when it is ready to respond, and sends the requested data packet. Up to four transactions are allowed to be outstanding at any given time.

Intel Pentium II Microprocessor

The Pentium II processor has several high-performance features that enhance performance:

•Dual Independent Bus architecture, which combines a dedicated 64-bit L2 cache bus (supporting level cache sizes of 256K or 512K), plus a 64-bit system bus with ECC that enables multiple simultaneous transactions (re- fer to above “split -transaction”).

•Intel MMX technology, which gives higher performance for media, com- munications and 3D applications.

•Dynamic execution to speed up software performance.

The Pentium II processor and level-2 cache memory are packaged in a self- contained, pre-sealed module, installed in a socket on the system board.

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