28 RS/6000 43P 7043 Models 150 and 260 Handbook
system interface of a 64-bit data bus and a 32-bit address bus. This highly
integrated chip acts as both a PCI bridge and a memory controller. It contains
the system bus arbitration, provides support for full memory coherency, and
pipelining of processor accesses.
Information may be routed from the memory chip to main memory, using the
memory bus, or to I/O devices using the I/O bus.
In the Model 150, the memory bus runs at 83 MHz. The memory subsystem
supports up to four industry-standard DIMM sockets with supported
capacities of 64, 128 and 256 MB. The memory DIMM can be populated in
any order. An ECC controller/buffer, running at 83 MHz, handles high
performance ECC operation with SDRAM memory, and parity operation on
the system bus. Single bit errors are corrected, while double bit errors are
detected.
For access to I/O devices, the PCI bus is used, running at 33 MHz. Devices
such as the integrated Ethernet adapter, the integrated Ultra SCSI controller
and the IBM Multiprocessor Interrupt Controller (MPIC) are all attached to the
PCI bus. This bus also leads to the PCI-to-ISA bridge, which the Model 150
uses as the system I/O bridge. The PCI-to-ISA bridge supports a PCI bus
controller interface to enhanced IDE drives, an ISA bus bridge, and an
XD-bus interface (for support of flash EPROM).
The ISA bus runs at 8 MHz and provides support for the following:
• Business audio controller
• Tablet port
• Native I/O controller (for diskette controller, serial ports, parallel port)
• 1 MB Flash ROM (to contain the IPLROS Open Firmware)