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The performance design of the z/Architecture enables the
entire server to support a new standard of performance for
applications through expanding upon a balanced system
approach. As CMOS technology has been enhanced to
support not only additional processing power, but also
more engines, the entire server is modifi ed to support the
increase in processing power. The I/O subsystem supports
a great amount of bandwidth through internal changes,
thus providing for larger and quicker data movement into
and out of the server. Support of larger amounts of data
within the server required improved management of stor-
age confi gurations made available through integration of
the software operating system and hardware support of
64-bit addressing. The combined balanced system effect
allows for increases in performance across a broad spec-
trum of work. However, due to the increased fl exibility in
the z990 model structure and resource management in
the system, it is expected that there will be larger perfor-
mance variability than has been previously seen by our
traditional customer set. This variability may be observed
in several ways. The range of performance ratings across
the individual LSPR workloads is likely to have a larger
spread than past processors. There will also be more
performance variation of individual LPAR partitions as the
impact of fl uctuating resource requirements of other parti-
tions can be more pronounced with the increased number
of partitions and additional CPs available on the z990. The
customer impact of this increased variability will be seen
as increased deviations of workloads from single-number-
metric based factors such as MIPS, MSUs and CPU time
chargeback algorithms. It is important to realize the z990
has been optimized to run many workloads at high utiliza-
tion rates.
It is also important to notice that the LSPR workloads for
z990 have been updated to refl ect more closely our cus-
tomers’ current and growth workloads. The traditional TSO
LSPR workload is replaced by a new, heavy Java tech-
nology-based online workload referred to as Trade2-EJB
(a stock trading application). The traditional CICS®/DB2®
LSPR online workload has been updated to have a Web-
frontend which then connects to CICS. This updated
workload is referred to as WEB/CICS/DB2 and is repre-
sentative of customers who Web-enable access to their
legacy applications. Continuing in the LSPR for z990 will
be the legacy online workload, IMS, and two legacy batch
workloads CB84 and CBW2. The z990 LSPR will provide
performance ratios for individual workloads as well as a
“default mixed workload” which is used to establish single-
number-metrics such as MIPS, MSUs and SRM constants.
The z990 default mixed workload will be composed of
equal amounts of fi ve workloads, Trade2-EJB, WEB/CICS/
DB2, IMS, CB84 and CBW2. Additionally, the z990 LSPR
will rate all z/Architecture processors running in LPAR
mode and 64-bit mode. The existing z900 processors have
all been re-measured using the new workloads — all run-
ning in LPAR mode and 64-bit mode.
Using the new LSPR ‘default mixed workload’, and with all
processors executing in 64-bit and LPAR mode, the follow-
ing results have been estimated: