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Inova ICP-PII 2002 Inova Computers GmbHPage 3-6 Doc. PD00581013.004, Table 3.04 Inovas ICP-PIII 32-Bit CompactPCI J2 Pin Assignment for Rear I/O (A)

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Interfaces

ICP-PIII

Table 3.04 Inova’s ICP-PIII 32-Bit CompactPCI J2 Pin Assignment for Rear I/O (A)

4) : 5V open collector signal (5V/100mA)

5) : Option “External Battery” (Note: battery must be removed from CPU board)

Ubat = +3.4V to +3.6V

6) : RS485 signals

Pin Nr Row A Row B Row C Row D Row E

J2-22 -----

J2-21 CLK6 GND ETH_TxF+ ETH_TxF- ETH_R45

J2-20 CLK5 GND COM 2-

GND ETH_R78

J2-19 GND GND COM 2+

ETH_RxF+ ETH_RxF-

J2-18 - - COM 1-

GND COM 1+

J2-17 - GND PRST# REQ6# GNT6#

J2-16 - -

GND (UBAT)

J2-15 - GND

REQ5# GNT5#

J2-14 - - - GND -

J2-13 - GND V(I/O) - -

J2-12 - -

GND -

J2-11 - GND V(I/O) - -

J2-10 - -

GND -

J2-09 - GND V(I/O) - -

J2-08 - - - GND -

J2-07

GND V(I/O) - -

J2-06 - - - GND -

J2-05 - GND V(I/O) - -

J2-04 V(I/O)

SPEAKER

4) - GND -

J2-03 CLK4 GND GNT3# REQ4# GNT4#

J2-02 CLK2 CLK3 SYSEN# GNT2# GNT3#

J2-01 CLK1 GND REQ1# GNT1# REQ2#

Contents

Main Page Preface Contents Page 3.1 CompactPCI Backplane .......... 3-10 3.2 Interfaces ............................. 3-12 A1 IPB-FPE8 CPU Extension ......... A-2 B1 ICP-HD CPU Extension ............. B-2 B1 IPM-ATA CPU Extension ........... B-2 C1 IPB-FPE12 CPU Extension ........ C-2 D1 IPB-RIO CPU Extension............ D-2 Unpacking and Special Handling Instructions 2002 Inova Computers GmbH Page 0-7Doc. PD00581013.004 Revision History Revision History Three Year Limited Warranty Product Overview Overview Contents 1.0 ICP-PIII CPU ........................... 1-2 1.1 Specifications ......................... 1-4 1.2 Configuration .......................... 1-6 1.3 Software ................................ 1-8 1.4 Hardware ............................. 1-10 1.0 ICP-PIII CPU Page 1.1 Specifications Page 1.2 Configuration Page 1.3 Software 1.31 Linux 1.32 VentureCom 1.33 Windows 2000 1.34 Windows CE 1.35 VxWorks 1.36 OS-9 x86 1.37 QNX 1.38 Jbed 1.4 Hardware 1.41 Block Diagram Figure 1.41 Block Diagram North Bridge Intel 82443BX South Bridge ALi 1543C 1.42 Connector Location Table 1.43 Connector Description Figure 1.42 Connector Locations 1.43 Connector Description Connector Description 1.44 Front-Panel Features Connector Description Interface Description & Location Page 1.45 Interface Positions Page 2.0 Memory Map Start Address Finish Address UMB Reservations for ISA Port Address Port Addressing COM1 3F8h COM2 2F8h LPT1 378h 2.1 I/O Mapped Peripherals I/O Address Description 2.2 Memory Mapped Peripherals 2.3 Interrupt Routing Interrupt Request Interrupt Vector Function/Assignment 2.4 Inova PIII Device List PCI Bus Number Device Number PCI Interrupt Routing Description 2.5 Interrupt Configuration CompactPCI Bus Interrupts 2.6 Timer / Counter Timer Function/Assignment 2.7 Watchdog Page Interfaces Interfaces Contents 3.0 CompactPCI J1/J2 Connector... 3-3 3.1 CompactPCI Backplane .......... 3-10 3.2 Interfaces ............................. 3-12 Page 3.0 CompactPCI J1/J2 Connector 3.01 CompactPCI Connector 3.02 ICP-PIII Connector J1 and J2 Pin Nr Row A Row B Row C Row D Row E 2002 Inova Computers GmbH Page 3-5Doc. PD00581013.004 Table 3.03 Inovas ICP-PIII 32-Bit CompactPCI J2 Pin Assignment (Standard) 2002 Inova Computers GmbHPage 3-6 Doc. PD00581013.004 Table 3.04 Inovas ICP-PIII 32-Bit CompactPCI J2 Pin Assignment for Rear I/O (A) 2002 Inova Computers GmbH Page 3-7Doc. PD00581013.004 Table 3.05 Inovas ICP-PIII 32-Bit CompactPCI J2 Pin Assignment for Rear I/O (B) decoupling (USB specification). connector. 2002 Inova Computers GmbHPage 3-8 Doc. PD00581013.004 Table 3.06 Inovas ICP-PIII 32-Bit CompactPCI J2 Pin Assignment for Rear I/O (C) decoupling (USB specification). connector. REAR I/O OPTION Rear I/O 3.1 CompactPCI Backplane Page 3.2 Interfaces 3.21 J7 & J12 Fast Ethernet Activity Link 81 Pin No. Signal 3.22 J17 VGA Interface Pin No. Signal 5 15 1 11 10 6 Refresh Rates (Hz) Page Page 3.25 J19 USB Interface Pin No. Signal 3.26 J15 FireWire Interface Pin No. Signal Page 3.31 Connecting the PIII to the Inova IPB-FPE8 2002 Inova Computers GmbH Page 3-21Doc. PD00581013.004 3.32 Connecting the PIII to the Inova ICP-HD-1 3.33 Connecting the PIII to the Inova IPB-FPE12 3.34 Connecting the PIII to the Inova IPB-FPE12 3.35 Connecting the PIII to the ICP-FD-1 IPB-FPE8 IPB-FPE8 Contents A1 IPB-FPE8 CPU Extension ......... A-2 A1 IPB-FPE8 CPU Extension A1.1 J11 Interface for COM1, Mouse & Keyboard A1.2 IPB-FPE8 & Front-panel (4HP or 8HP) J11 Pin 1 A1.3 Stand-Alone IPB-FPE8 A1.4 IPB-FPE8MS (Theme Variation) Connector Description 2 3 4 5 A1.5 IPB-FPE8MS Description Connector Description A1.6 Keyboard Interface A1.7 Mouse Interface A1.8 COM1 Interface Page ICP-HD ICP-HD Contents B1 ICP-HD CPU Extension ............. B-2 B1 ICP-HD CPU Extension B1.1 J11, J13 Interfaces B1.2 ICP-HD-1 & Front-panel (4HP or 8HP) B1.3 IDE Carrier Board ICP-HD-1 B1.4 ICP-HDE8MS (Theme Variation) Connector Description Connector Description B1.5 ICP-HDE8MS Description B1.6 Keyboard Interface B1.7 Mouse Interface B1.8 COM1 & COM 2 Interfaces IPM-ATA IPM-ATA B1 IPM-ATA CPU Extension ........... B-2 B1 IPM-ATA CPU Extension B1.1 J1 Interfaces B1.1 J1 Interfaces (Contd.) Page Page Page B1.5 Device Compatibility Test Position Compact FLASH Card Jumper Result Page IPB-FPE12 IPB-FPE12 Contents C1 IPB-FPE12 CPU Extension ........ C-2 C1 IPB-FPE12 CPU Extension C1.1 J13 Interface for LPT1 & COM2 C1.2 IPB-FPE12 & Front-panel (4HP or 12HP) J13 C1.3 LPT1 & COM2 Piggyback Connector Description C1.4 LPT1 Interface C1.5 COM2 Interface Page D1 IPB-RIO CPU Extension D1.1 IPB-RIO-HD-FD IDE-Connection Floppy D D1.3 IPB-RIO-C-SHORT REAR I/O OPTION Rear I/O - 'C'