80C186EA/80C188EA, 80L186EA/80L188EA

Table 3. Pin Descriptions (Continued)

 

 

 

 

Pin

Pin

Input

Output

Description

 

Name

Type

Type

States

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MCS0/PEREQ

I/O

A(L)

H(1)

These pins provide a multiplexed function. If enabled,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

these pins normally comprise a block of Mid-Range Chip

 

MCS1/ERROR

 

 

R(1)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Select outputs which will go active whenever the address

 

MCS2

 

 

 

 

 

P(1)

 

 

 

of a memory bus cycle is within the address limitations

 

MCS3/NCS

 

 

 

 

 

 

 

programmed by the user. In Numerics Mode (80C186EA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

only), three of the pins become handshaking pins for the

 

 

 

 

 

 

 

 

 

 

 

 

 

 

80C187. The CoProcessor REQuest input signals that a

 

 

 

 

 

 

 

 

 

 

 

 

 

 

data transfer is pending. ERROR is an input which

 

 

 

 

 

 

 

 

 

 

 

 

 

 

indicates that the previous numerics coprocessor

 

 

 

 

 

 

 

 

 

 

 

 

 

 

operation resulted in an exception condition. An interrupt

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type 16 is generated when ERROR is sampled active at

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the beginning of a numerics operation. Numerics

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Coprocessor Select is an output signal generated when

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the processor accesses the 80C187.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCS4:0

O

 

H(1)

Peripheral Chip Selects go active whenever the address

 

 

 

 

 

 

 

 

 

 

 

 

 

R(1)

of a memory or I/O bus cycle is within the address

 

 

 

 

 

 

 

 

 

 

 

 

 

P(1)

limitations programmed by the user.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCS5/A1

O

 

H(1)/H(X)

These pins provide a multiplexed function. As additional

 

 

 

 

 

 

 

 

 

Peripheral Chip Selects, they go active whenever the

 

PCS6/A2

 

 

R(1)

 

 

 

 

 

 

 

 

 

 

 

 

 

P(1)

address of a memory or I/O bus cycle is within the

 

 

 

 

 

 

 

 

 

 

 

 

 

address limitations by the user. They may also be

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

programmed to provide latched Address A2:1 signals.

 

 

 

 

 

 

 

 

 

 

T0OUT

O

 

H(Q)

Timer OUTput pins can be programmed to provide a

 

T1OUT

 

 

R(1)

single clock or continuous waveform generation,

 

 

 

 

 

 

 

 

 

 

 

 

 

P(Q)

depending on the timer mode selected.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

T0IN

I

A(L)

 

Timer INput is used either as clock or control signals,

 

T1IN

 

A(E)

 

depending on the timer mode selected.

 

 

 

 

 

 

 

 

 

 

DRQ0

I

A(L)

 

DMA ReQuest is asserted by an external request when it

 

DRQ1

 

 

 

is prepared for a DMA transfer.

 

 

 

 

 

 

 

 

 

 

INT0

 

 

I

A(E,L)

 

Maskable INTerrupt input will cause a vector to a specific

 

INT1/SELECT

 

 

 

Type interrupt routine. To allow interrupt expansion, INT0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

and/or INT1 can be used with INTA0 and INTA1 to

 

 

 

 

 

 

 

 

 

 

 

 

 

 

interface with an external slave controller. INT1 becomes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SELECT when the ICU is configured for Slave Mode.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INT2/INTA0

I/O

A(E,L)

H(1)

These pins provide multiplexed functions. As inputs, they

 

 

 

 

 

 

 

provide a maskable INTerrupt that will cause the CPU to

 

INT3/INTA1/IRQ

 

 

R(Z)

 

 

 

 

 

 

 

 

 

 

 

 

 

P(1)

vector to a specific Type interrupt routine. As outputs,

 

 

 

 

 

 

 

 

 

 

 

 

 

each is programmatically controlled to provide an

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INTerrupt Acknowledge handshake signal to allow

 

 

 

 

 

 

 

 

 

 

 

 

 

 

interrupt expansion. INT3/INTA1 becomes IRQ when the

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ICU is configured for Slave Mode.

 

 

 

 

 

 

 

N.C.

 

 

 

No Connect. For compatibility with future products, do not

 

 

 

 

 

 

 

 

 

 

 

 

 

 

connect to these pins.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NOTE:

Pin names in parentheses apply to the 80C188EA and 80L188EA.

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Image 14
Intel 80C188EA MCS0/PEREQ, MCS1/ERROR, MCS2, MCS3/NCS, PCS5/A1, PCS6/A2, T0OUT, T1OUT, T0IN, T1IN, DRQ0, DRQ1, INT0
Page 13 Page 15

80L186EA, 80L188EA, 80C186EA, 80C188EA specifications

The Intel 80C188EA, 80C186EA, 80L188EA, and 80L186EA microprocessors represent significant developments in the realm of embedded computing during the 1980s. These processors are part of Intel's x86 architecture, designed to cater to a variety of industrial applications, including automotive and telecommunications.

The 80C188EA and 80C186EA are CMOS variants that offer enhanced power efficiency and reduced heat generation compared to their NMOS predecessors. Operating at clock speeds of up to 25 MHz, these processors are known for their performance in real-time applications. The 80C188EA features a 16-bit data bus and a 16-bit address bus, which can support up to 1 MB of addressable memory. It also boasts an extended instruction set for greater computing flexibility, making it suitable for intricate tasks in embedded systems.

Similarly, the 80C186EA is characterized by its 16-bit architecture, but it includes additional on-chip memory management capabilities. This processor can handle 256 KB of memory directly and supports paged memory management, facilitating efficient multitasking and resource sharing in complex applications. Its integrated DMA controller and interrupt controller allow for superior handling of peripheral devices, making it ideal for real-time processing requirements.

On the other hand, the 80L188EA and 80L186EA are low-power variants optimized for battery-operated designs. These microprocessors are tailored for applications where power consumption is critical. The 80L188EA retains the essential features of the 80C188EA but operates at lower voltage levels, thus allowing for longer operational life in portable devices. The 80L186EA similarly benefits from reduced power consumption, taking advantage of its energy-efficient design to enhance durability in industrial automation scenarios.

All four processors leverage Intel's established x86 architecture, enabling a wide range of software compatibility. Their built-in support for real-time interrupt handling and I/O operations provides developers with valuable tools for building reliable embedded systems. Additionally, they feature on-chip oscillators and timers, further streamlining design requirements and reducing the need for external components.

Overall, the Intel 80C188EA, 80C186EA, 80L188EA, and 80L186EA processors are ideal for diverse applications in embedded systems. Their blend of processing power, energy efficiency, and versatility continues to influence the design of modern electronic devices, underscoring Intel's pivotal role in advancing microprocessor technology.
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