Intel 80C186EA, 80C188EA, 80L186EA, 80L188EA AC SPECIFICATIONS Relative Timings (80C186EA25/20/13, 80L186EA13/8)

80C186EA/80C188EA, 80L186EA/80L188EA

AC SPECIFICATIONS (Continued)

Relative Timings (80C186EA25/20/13, 80L186EA13/8)

Symbol Parameter Min Max Unit Notes

RELATIVETIMINGS

TLHLL ALERising to ALE Falling T b15 ns

TAVLL AddressValid to ALE Falling (/2Tb10 ns

TPLLL ChipSelects Valid to ALE Falling (/2Tb10 ns 1

TLLAX AddressHold from ALE Falling (/2Tb10 ns

TLLWL ALEFalling to WR Falling (/2Tb15 ns 1

TLLRL ALEFalling to RD Falling (/2Tb15 ns 1

TRHLH RDRising to ALE Rising (/2Tb10 ns 1

TWHLH WRRising to ALE Rising (/2Tb10 ns 1

TAFRL AddressFloat to RD Falling 0 ns

TRLRH RDFalling to RD Rising (2*T) b5ns2

WLWH WRFalling to WR Rising (2*T) b5ns2

RHAV RDRising to Address Active T b15 ns

TWHDX OutputData Hold after WR Rising T b15 ns

TWHDEX WRRising to DEN Rising (/2Tb10 ns 1

TWHPH WRRising to Chip Select Rising (/2Tb10 ns 1, 4

TRHPH RDRising to Chip Select Rising (/2Tb10 ns 1,4

TPHPL CSInactive to CS Active (/2Tb10 ns 1

TDXDL DENInactive to DT/R Low 0 ns 5

TOVRH ONCE(UCS, LCS) Active to RESIN Rising T ns 3

TRHOX ONCE(UCS, LCS) to RESIN Rising T ns 3

NOTES:

1. Assumes equal loading on both pins.

2. Can be extended using wait states.

3. Not tested.

4. Not applicable to latched A2:1. These signals change only on falling T1.

5. For write cycle followed by read cycle.

6. Operating conditions for 25 MHz are 0§Ctoa

70§C, VCC e5.0V g10%.