Intel 80C186EA, 80C188EA, 80L186EA, 80L188EA DC SPECIFICATIONS (80C186EA/80C188EA)

80C186EA/80C188EA, 80L186EA/80L188EA

DC SPECIFICATIONS (80C186EA/80C188EA)

Symbol Parameter Min Max Units Conditions

VCC SupplyVoltage 4.5 5.5 V

VIL InputLow Voltage for All Pins b0.5 0.3VCC V

VIH InputHigh Voltage for All Pins 0.7 VCC VCC a0.5 V

VOL OutputLow Voltage 0.45 V IOL e3 mA (min)

VOH OutputHigh Voltage VCC b0.5 V IOH eb

2mA (min)

VHYR InputHysterisis on RESIN 0.30 V

IIL1 InputLeakage Current (except g10 mA0V

IN sVCC

RD/QSMD,UCS, LCS, MCS0/PEREQ,

MCS1/ERROR,LOCK and TEST/BUSY)

IIL2 InputLeakage Current b275 mAV

IN e0.7VCC

(RD/QSMD,UCS, LCS, MCS0/PEREQ, (Note1)

MCS1,ERROR, LOCK and TEST/BUSY

IOL OutputLeakage Current g10 mA0.45 sVOUT sVCC

(Note2)

ICC SupplyCurrent Cold (RESET)

80C186EA25/80C188EA25 105 mA (Notes3, 5)

80C186EA20/80C188EA20 90 mA

80C186EA13/80C188EA13 65 mA

IID SupplyCurrent In Idle Mode

80C186EA25/80C188EA25 90 mA (Note 5)

80C186EA20/80C188EA20 70 mA

80C186EA13/80C188EA13 46 mA

IPD SupplyCurrent In Powerdown Mode

80C186EA25/80C188EA25 100 mA (Note5)

80C186EA20/80C188EA20 100 mA

80C186EA13/80C188EA13 100 mA

COUT OutputPin Capacitance 0 15 pF TFe1 MHz (Note 4)

CIN InputPin Capacitance 0 15 pF TFe1 MHz

NOTES:

1. RD/QSMD, UCS, LCS, MCS0/PEREQ, MCS1/ERROR, LOCK and TEST/BUSY have internal pullups that are only acti-

vated during RESET. Loading these pins above IOL eb

275 mA will cause the processor to enter alternate modes of

operation.

2. Output pins are floated using HOLD or ONCE Mode.

3. Measured at worst case temperature and VCC with all outputs loaded as specified in the AC Test Conditions, and with the

device in RESET (RESIN held low). RESET is worst case for ICC.

4. Output capacitance is the capacitive load of a floating output pin.

5. Operating conditions for 25 MHz are 0§Ctoa

70§C, VCC e5.0V g10%.