Manuals / Intel / Computer Equipment / Computer Hardware

Intel 80L186EA, 80L188EA, 80C188EA BUS Cycle Waveforms, Read, Fetch and Refresh Cycle Waveform

Models: 80L186EA 80L188EA 80C186EA 80C188EA

1 50

Download 50 pages 36.73 Kb

Page 36

80C186EA/80C188EA, 80L186EA/80L188EA

BUS CYCLE WAVEFORMS

Figures 17 through 23 present the various bus cycles that are generated by the processor. What is shown in the figure is the relationship of the various bus signals to CLKOUT. These figures along with the information present in AC Specifications allow the user to determine all the critical timing analysis needed for a given application.

272432-17

NOTES:

1.During the data phase of the bus cycle, A19/S6 is driven high for a DMA or refresh cycle.

2.Pin names in parentheses apply to the 80C188EA.

Figure 17. Read, Fetch and Refresh Cycle Waveform

36

36

Image 36

Intel 80L186EA, 80L188EA, 80C188EA, 80C186EA specifications BUS Cycle Waveforms, Read, Fetch and Refresh Cycle Waveform

Contents

BIT HIGH-INTEGRATION Embedded Processors Contentspage C186EA/80C188EA Block Diagram Introduction 80C186EA Core ArchitectureBus Interface Unit Clock GeneratorTimer/Counter Unit 80C186EA Peripheral ArchitectureInterrupt Control Unit Crystal Connection Clock ConnectionPeripheral Control Block Registers Power Management DMA Control UnitChip-Select Unit Refresh Control UnitDifferences Between the 80C186XL and the 80C186EA Package Information Pin DescriptionsPlcc QFP EiajRWH Clkin OscoutResin ResoutALE/QS0 BHERfsh RD/QSMDWR/QS1 ArdySrdy DENMCS1/ERROR MCS0/PEREQMCS2 MCS3/NCS80C186EA Pinout AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7Lead Plcc Pinout Diagram Plcc Package Location with Pin NamesQFP Eiaj Pin Names with Package Location Quad Flat Pack Eiaj Pinout Diagram QFP Eiaj Package Location with Pin NamesSqfp Pin Functions with Package Location Sqfp Pin Locations with Pin NamesHlda Hold Srdy Lock TEST/BUSY NMI INT0 INT1/SELECT UCS LCS PCS6/A2 PCS5/A1 PCS4 PCS3 PCS2 PCS1Package Thermal Specifications 400 600 800 1000 CA PlccCA QFP 60.5 CA Sqfp Electrical Specifications Voltage on Other Pins with RespectAbsolute Maximum Ratings Recommended ConnectionsDC Specifications 80C186EA/80C188EA RD/QSMD, UCS, LCS, MCS0/PEREQDC Specifications 80L186EA/80L188EA RD/QSMD, UCS, LCS, MCS0Power e V c I e V2 c Cdev c f ICC e Iccs e V c Cdev c f Pdtmr PIN Delay CalculationICC Versus Frequency and Voltage AC Specifications AC Characteristics-80C186EA25/80C186EA20/80C186EA13HOLD, PEREQ, Error Synchronous InputsTEST, NMI, INT30 T10IN, Ardy SRDY, DRQ10AC Characteristics-80L186EA13/80L186EA8 ALE, LockMCS30, LCS, UCS LOCK, RESOUT, Hlda T0OUT, T1OUTTEST, NMI, INT30, T10IN, Ardy AD150 AD70, ARDY, SRDY, DRQ10Relative Timings AC Test Conditions AC Timing WaveformsOutput Delay and Float Waveform Relative Signal Waveform Reset Derating CurvesPowerup Reset Waveforms Warm Reset Waveforms BUS Cycle Waveforms Read, Fetch and Refresh Cycle WaveformWrite Cycle Waveform Halt Cycle Waveform Inta Cycle Waveform HOLD/HLDA Waveform Dram Refresh Cycle During Hold Acknowledge Ready Waveform 80C186EA/80C188EA Execution Timings Instruction SET Summary Data TransferInstruction SET Summary ArithmeticLogic String Manipulation Within seg adding immed to SP 010 DX 010 DL 100 SP101 BP 101 CH 110 SI 110 DH 111 DI 111 BH Revision History Errata