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Intel 80L188EA, 80L186EA 010 DX 010 DL, 100 SP, 101 BP 101 CH 110 SI 110 DH 111 DI 111 BH

Models: 80L186EA 80L188EA 80C186EA 80C188EA

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80C186EA/80C188EA, 80L186EA/80L188EA

INSTRUCTION SET SUMMARY (Continued)

 

 

 

80C186EA

80C188EA

 

 

 

Function

 

Format

Clock

Clock

Comments

 

 

 

Cycles

Cycles

 

 

 

PROCESSOR CONTROL

 

 

 

 

 

 

 

CLC e Clear carry

 

 

 

 

 

 

 

1 1 1 1 1 0 0 0

 

2

2

 

 

 

CMC e Complement carry

1 1 1 1 0 1 0 1

 

2

2

 

 

 

STC e Set carry

1 1 1 1 1 0 0 1

 

2

2

 

 

 

CLD e Clear direction

1 1 1 1 1 1 0 0

 

2

2

 

 

 

STD e Set direction

1 1 1 1 1 1 0 1

 

2

2

 

 

 

CLI e Clear interrupt

1 1 1 1 1 0 1 0

 

2

2

 

 

 

STI e Set interrupt

1 1 1 1 1 0 1 1

 

2

2

 

 

 

HLT e Halt

1 1 1 1 0 1 0 0

 

2

2

 

 

 

WAIT e Wait

 

 

 

 

 

1 0 0 1 1 0 1 1

 

6

6

if

TEST

e 0

LOCK e Bus lock prefix

1 1 1 1 0 0 0 0

 

2

2

 

 

 

NOP e No Operation

1 0 0 1 0 0 0 0

 

3

3

 

 

 

 

(TTT LLL are opcode to processor extension)

 

 

 

 

 

Shaded areas indicate instructions not available in 8086/8088 microsystems.

NOTE:

*Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers.

The Effective Address (EA) of the memory operand is computed according to the mod and r/m fields:

if mod

e

11 then r/m is treated as a REG field

if mod

e

00 then DISP e 0*, disp-low and disp-

 

 

high are absent

if mod

e

01 then DISP e disp-low sign-ex-

 

 

tended to 16-bits, disp-high is absent

if mod

e

10 then DISP e disp-high: disp-low

if r/m

e

000 then EA e (BX) a (SI) a DISP

if r/m

e

001 then EA e (BX) a (DI) a DISP

if r/m

e

010 then EA e (BP) a (SI) a DISP

if r/m

e

011 then EA e (BP) a (DI) a DISP

if r/m

e

100 then EA e (SI) a DISP

if r/m

e

101 then EA e (DI) a DISP

if r/m

e

110 then EA e (BP) a DISP*

if r/m

e

111 then EA e (BX) a DISP

DISP follows 2nd byte of instruction (before data if required)

*except if mod e 00 and r/m e 110 then EA e disp-high: disp-low.

EA calculation time is 4 clock cycles for all modes, and is included in the execution times given whenev- er appropriate.

Segment Override Prefix

0 0 1 reg 1 1 0

reg is assigned according to the following:

Segment

reg Register

00ES

01CS

10SS

11DS

REG is assigned according to the following table:

16-Bit (w e 1)

8-Bit (w e 0)

000 AX

000 AL

001 CX

001 CL

010 DX

010 DL

011 BX

011 BL

100 SP

100 AH

101 BP

101 CH

110 SI

110 DH

111 DI

111 BH

The physical addresses of all operands addressed by the BP register are computed using the SS seg- ment register. The physical addresses of the desti- nation operands of the string primitive operations (those addressed by the DI register) are computed using the ES segment, which may not be overridden.

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Intel 80L188EA, 80L186EA, 80C188EA, 80C186EA specifications 010 DX 010 DL, 100 SP, 101 BP 101 CH 110 SI 110 DH 111 DI 111 BH
Page 48 Page 50

80L186EA, 80L188EA, 80C186EA, 80C188EA specifications

The Intel 80C188EA, 80C186EA, 80L188EA, and 80L186EA microprocessors represent significant developments in the realm of embedded computing during the 1980s. These processors are part of Intel's x86 architecture, designed to cater to a variety of industrial applications, including automotive and telecommunications.

The 80C188EA and 80C186EA are CMOS variants that offer enhanced power efficiency and reduced heat generation compared to their NMOS predecessors. Operating at clock speeds of up to 25 MHz, these processors are known for their performance in real-time applications. The 80C188EA features a 16-bit data bus and a 16-bit address bus, which can support up to 1 MB of addressable memory. It also boasts an extended instruction set for greater computing flexibility, making it suitable for intricate tasks in embedded systems.

Similarly, the 80C186EA is characterized by its 16-bit architecture, but it includes additional on-chip memory management capabilities. This processor can handle 256 KB of memory directly and supports paged memory management, facilitating efficient multitasking and resource sharing in complex applications. Its integrated DMA controller and interrupt controller allow for superior handling of peripheral devices, making it ideal for real-time processing requirements.

On the other hand, the 80L188EA and 80L186EA are low-power variants optimized for battery-operated designs. These microprocessors are tailored for applications where power consumption is critical. The 80L188EA retains the essential features of the 80C188EA but operates at lower voltage levels, thus allowing for longer operational life in portable devices. The 80L186EA similarly benefits from reduced power consumption, taking advantage of its energy-efficient design to enhance durability in industrial automation scenarios.

All four processors leverage Intel's established x86 architecture, enabling a wide range of software compatibility. Their built-in support for real-time interrupt handling and I/O operations provides developers with valuable tools for building reliable embedded systems. Additionally, they feature on-chip oscillators and timers, further streamlining design requirements and reducing the need for external components.

Overall, the Intel 80C188EA, 80C186EA, 80L188EA, and 80L186EA processors are ideal for diverse applications in embedded systems. Their blend of processing power, energy efficiency, and versatility continues to influence the design of modern electronic devices, underscoring Intel's pivotal role in advancing microprocessor technology.