80C186EA/80C188EA, 80L186EA/80L188EA
272432 – 23
NOTES:
1.Generalized diagram for READ or WRITE.
2.ARDY low by either edge causes a wait state. Only rising ARDY is fully synchronized.
3.SRDY low causes a wait state. SRDY must meet setup and hold times to ensure correct device operation.
4.Either ARDY or SRDY active high will terminate a bus cycle.
5.Pin names in parentheses apply to the 80C188EA.
Figure 23. Ready Waveform
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42
