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Intel 80L186EA Package Thermal Specifications, 400 600 800 1000 CA Plcc, CA QFP 60.5 CA Sqfp

Models: 80L186EA 80L188EA 80C186EA 80C188EA

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80C186EA/80C188EA, 80L186EA/80L188EA

272432 – 7

Figure 7. Shrink Quad Flat Pack (SQFP) Pinout Diagram

NOTES:

1.XXXXXXXXD indicates the Intel FPO number.

2.Pin names in parentheses apply to the 80C188EA.

PACKAGE THERMAL

SPECIFICATIONS

The 80C186EA/80L186EA is specified for operation when TC (the case temperature) is within the range of 0§C to 85§C (PLCC package) or 0§C to 106§C (QFP-EIAJ) package. TC may be measured in any environment to determine whether the processor is within the specified operating range. The case tem- perature must be measured at the center of the top surface.

TA (the ambient temperature) can be calculated from iCA (thermal resistance from the case to ambi- ent) with the following equation:

TA e TC - P c iCA

Typical values for iCA at various airflows are given in Table 10.

P (the maximum power consumption, specified in watts) is calculated by using the maximum ICC as tabulated in the DC specifications and VCC of 5.5V.

Table 10. Thermal Resistance (iCA) at Various Airflows (in §C/Watt)

		Airflow Linear ft/min (m/sec)

	0	200	400	600	800	1000
	(0)	(1.01)	(2.03)	(3.04)	(4.06)	(5.07)

iCA (PLCC)	29	25	21	19	17	16.5
iCA (QFP)	66	63	60.5	59	58	57
iCA (SQFP)	70

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Intel 80L186EA, 80L188EA, 80C188EA, 80C186EA Package Thermal Specifications, 400 600 800 1000 CA Plcc, CA QFP 60.5 CA Sqfp

Contents

BIT HIGH-INTEGRATION Embedded Processors Contentspage C186EA/80C188EA Block Diagram Introduction 80C186EA Core ArchitectureBus Interface Unit Clock GeneratorTimer/Counter Unit 80C186EA Peripheral ArchitectureInterrupt Control Unit Crystal Connection Clock ConnectionPeripheral Control Block Registers Power Management DMA Control UnitChip-Select Unit Refresh Control UnitDifferences Between the 80C186XL and the 80C186EA Package Information Pin DescriptionsPlcc QFP EiajRWH Clkin OscoutResin ResoutALE/QS0 BHERfsh RD/QSMDWR/QS1 ArdySrdy DENMCS1/ERROR MCS0/PEREQMCS2 MCS3/NCS80C186EA Pinout AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7Lead Plcc Pinout Diagram Plcc Package Location with Pin NamesQFP Eiaj Pin Names with Package Location Quad Flat Pack Eiaj Pinout Diagram QFP Eiaj Package Location with Pin NamesSqfp Pin Functions with Package Location Sqfp Pin Locations with Pin NamesHlda Hold Srdy Lock TEST/BUSY NMI INT0 INT1/SELECT UCS LCS PCS6/A2 PCS5/A1 PCS4 PCS3 PCS2 PCS1CA QFP 60.5 CA Sqfp Package Thermal Specifications400 600 800 1000 CA Plcc Electrical Specifications Voltage on Other Pins with RespectAbsolute Maximum Ratings Recommended ConnectionsDC Specifications 80C186EA/80C188EA RD/QSMD, UCS, LCS, MCS0/PEREQDC Specifications 80L186EA/80L188EA RD/QSMD, UCS, LCS, MCS0ICC Versus Frequency and Voltage Power e V c I e V2 c Cdev c f ICC e Iccs e V c Cdev c fPdtmr PIN Delay Calculation AC Specifications AC Characteristics-80C186EA25/80C186EA20/80C186EA13HOLD, PEREQ, Error Synchronous InputsTEST, NMI, INT30 T10IN, Ardy SRDY, DRQ10AC Characteristics-80L186EA13/80L186EA8 ALE, LockMCS30, LCS, UCS LOCK, RESOUT, Hlda T0OUT, T1OUTTEST, NMI, INT30, T10IN, Ardy AD150 AD70, ARDY, SRDY, DRQ10Relative Timings AC Test Conditions AC Timing WaveformsOutput Delay and Float Waveform Relative Signal Waveform Reset Derating CurvesPowerup Reset Waveforms Warm Reset Waveforms BUS Cycle Waveforms Read, Fetch and Refresh Cycle WaveformWrite Cycle Waveform Halt Cycle Waveform Inta Cycle Waveform HOLD/HLDA Waveform Dram Refresh Cycle During Hold Acknowledge Ready Waveform 80C186EA/80C188EA Execution Timings Instruction SET Summary Data TransferInstruction SET Summary ArithmeticLogic String Manipulation Within seg adding immed to SP 101 BP 101 CH 110 SI 110 DH 111 DI 111 BH 010 DX 010 DL100 SP Revision History Errata