Chapter 18 CPU Baseboard: Description/Setting Configuration Jumpers
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I/O Interface

The CPU baseboard interfaces with the PHP I/O baseboard and memory modules through the
grand connector on the midplane. The I/O interface portion of the grand connector provides the
primary and secondary expander buses, server management signals, front panel signals, and legacy
signals. The expander buses provide source-synchronous, high-speed bidirectional point-to-point
links between the CPU baseboard and the PHP I/O baseboard. Each expander bus has enough
bandwidth for two 32-bit, 33 MHz PCI buses or one 64-bit, 33 MHz PCI bus. The expander buses
use AGTL+ signaling technology.

Front Side Bus

The front side bus (FSB) is an ECC protected 64-bit bus that uses GTL+ signaling technology; it
runs at 100 MHz. The FSB requires termination modules in each unused Slot 2 connector. When
installing processors, always install them in sequence by starting with processor connector 1, then
connector 2, and so on—bottom connector to top connector. For example, in a dual processor
server, connectors 1 and 2 contain processors while connectors 3 and 4 contain terminator
modules.

Front Side Bus Termina tor Module

The FSB terminator module provides:
• the necessary termination for the AGTL+ signals on the FSB
• correct handling of JTAG scan signals