Chapter 18 CPU Baseboard: Description/Setting Configuration Jumpers
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CPU Baseboard Connectors

Memory Connectors, J23 and J20:Rows A, B, and C

Signal Pin Signal Pin Signal Pin
MD_L(35) A1 GND B1 MD_L(34) C1
GND A2 MD_L(32) B2 GND C2
MD_L(30) A3 GND B3 DSTBN_L(1) C3
GND A4 MD_L(28) B4 GND C4
MD_L(26) A5 GND B5 DSTBP_L(1) C5
GND A6 MD_L(24) B6 GND C6
MD_L(22) A7 GND B7 MD_L(21) C7
GND A8 GND B8 GND C8
MUXCLK0[A,B] A9 GND B9 MD_L(17) C9
GND A10 GND B10 GND C10
MRESET_L A11 GND B11 Reserved C11
GND A12 MD_L(16) B12 GND C12
MD_L(14) A13 GND B13 MD_L(13) C13
GND A14 MD_L(11) B14 GND C14
MD_L(9) A15 GND B15 DSTBP_L(0) C15
GND A16 MD_L(7) B16 GND C16
MD_L(5) A17 GND B17 DSTBN_L(0) C17
GND A18 MD_L(3) B18 GND C18
MD_L(2) A19 GND B19 MD_L(1) C19
GND A20 MD_L(0) B20 GND C20
MEM[A,B ]_ TCK A21 GND B 21 MEMA_TDI C21
GND A22 MEM[A,B]_ TRST_L B22 GND C22
MA_(12) A23 GND B23 MA_L(11) C23
GND A24 MA_L(9) B24 GND C24
MA_L(7) A25 GND B25 MA_L(6) C25
GND A26 MA_L(4) B26 GND C26
MA_L(3) A27 GND B27 MA_L(2) C27
GND A28 MA_L(1) B28 GND C28
MA_L(0) A29 GND B29 CSTB_L C29
GND A30 CMND1_L B30 GND C30
BANK1_L A31 GND B31 BANK2_L C31
GND A32 CARD[0,1]_L B32 GND C32
continued