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Intel AI5VG user manual Bank0, Bank1, Total Memory, SIMM1, SIMM2, SIMM3, SIMM4

Models: AI5VG

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Chapter 3 Hardware Description

(1)72-pin SIMM (5V) EDO DRAM

Bank0		Bank1		Total Memory
(SIMM1, SIMM2)		(SIMM3, SIMM4)
4MB×	2	-----		8MB
8MB×	2	-----		16MB
16MB× 2		-----		32MB
32MB× 2		-----		64MB
64MB× 2		-----		128MB
4MB×	2	4MB×	2	16MB
8MB×	2	4MB×	2	24MB
16MB× 2		4MB×	2	40MB
32MB× 2		4MB×	2	72MB
64MB× 2		4MB×	2	136MB
8MB×	2	8MB×	2	32MB
16MB× 2		8MB×	2	48MB
32MB× 2		8MB×	2	80MB
64MB× 2		8MB×	2	144MB
16MB× 2		16MB× 2		64MB
32MB× 2		16MB× 2		96MB
64MB× 2		16MB× 2		160MB
32MB× 2		32MB× 2		128MB
64MB× 2		32MB× 2		192MB
64MB× 2		64MB× 2		256MB

AI5VG Pentium VP3 Baby AT Motherboard User’s Manual

Page 11

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Intel AI5VG user manual Bank0, Bank1, Total Memory, SIMM1, SIMM2, SIMM3, SIMM4

Contents

Pentium VP3 Baby AT Motherboard AI5VGUser’s Manual Page Chapter 4 Hardware Settings ContentsChapter 6 BIOS Configuration •Hardware Description •Hardware Settings ChecklistChapter 1 Introduction •Introduction •SpecificationsMain Memory Chapter 2 SpecificationsMain Processor L2 CacheWindows 95 Shut-Down BIOSCPU Temperature Sensor Onboard Bus Mastering EIDEChapter 3 Hardware Description Chapter 3 Hardware Description Figure 1: Layout of the AI5VG MotherboardChapter 3 Hardware Description 3.1 Processor and CPU Voltage3.2 L2 Cache Memory 3.3 Main MemorySIMM1, SIMM2 Bank0Bank1 Total MemoryTotal Memory 3.4 BIOSBank0 DIMM2 Bank1 DIMM13. Power Management 3.7 Onboard CPU Temperature Sensor3.5 Onboard PCI EIDE 3.6 Onboard Multi-I/ODevice Description 3.8 I/O Port Address Map3.9 DMA Channels AddressFunction 3.10 Interrupt Request Lines IRQ3.11 Accelerated Graphics Port AGP Slot LevelChapter 4 Hardware Settings Chapter 4 Hardware Settings Figure 2: Jumper Locations of the AI5VGP55C = Pentium with MMX technology Bus ClockMutiplier CPU FREQBus Clock Bus ClockMutiplier CPU FREQBus Clock 4.2 SW21-4:CPU Voltage SelectorFor Dual Voltage CPU Intel P55C, Cyrix 6x86L/MX, AMD K63.3V Function 4.3 JP5: Clear CMOS SelectionFunction Chapter 5 Installation Chapter 5 Installation Figure 3: Connector Location on the AI5VGWire Color 5.1 I/O ConnectorsFigure 4: Orientation of the I/O Connector 5.2 J3: AT Power Supply ConnectorSignal Name 5.3 J2: ATX Power Supply Connector5.4 J1, J4: AT Keyboard and PS/2 Mouse Connectors Signal NameSignal Name 5.6 J8: Floppy Drive Connector5.5 J7, J6: Serial Ports Signal NameSignal Name 5.7 J9, J11: EIDE ConnectorsJ9: Primary IDE Connector Signal NameSignal Name 5.8 J10: Parallel Port Connector5.9 J15: IrDA Connector 5.10 J5: USB ConnectorPin # Signal Name 5.11 J13 Wake on LAN Connector5.12 J14: CPU Fan Power Connector 5.13 J20 Front Bezel ConnectorSignal Name Speaker: Pins 1 -Signal Name Power LED and Keylock: Pins 11 -J20 Pin # Reset Switch: Pins 9 andSignal Name Chapter 6 BIOS Configuration Cache Rd+CPU Wt Pipeline IDE Primary/Secondary Master/Slave PIO Press <DEL> to Enter Setup 6.1 BIOS Introduction6.2 BIOS Setup Chapter 7 LANDesk User Guide STANDARD CMOS SETUPDate 6.3 Standard CMOS SetupCYLS MODE for IDE HDD only : AutoTime Primary HDDs / Secondary HDDsHalt On Floppy 3 Mode SupportDrive A / Drive B VideoCPU Internal Cache / External Cache 6.4 BIOS Features SetupVirus Warning Boot Up NumLock Status Quick Power On Self TestBoot Sequence Boot Up Floppy SeekTypematic Rate Chars/Sec Typematic Rate SettingTypematic Delay Msec Video BIOS ShadowSustained 3T Write 6.5 Chipset Features SetupBank DRAM Timing DRAM Read PipelineMemory Hole at 15MB Addr Video BIOS CacheableSystem BIOS Cacheable Cache TimingPower Management 6.6 Power Management SetupPM Control by APM HDD Power DownDoze Mode Suspend ModeChapter 7 LANDesk User Guide PM EventsResources Controlled by 6.7 PNP/PCI ConfigurationPNP OS Installed Reset Configuration DataPCI Dynamic Bursting PCI Delay TransactionPCI#2 Access #1 Retry CPU to PCI Write BufferChapter 7 LANDesk User Guide PCI IDE IRQ Map ToChapter 7 LANDesk User Guide 6.8 Load BIOS Defaults6.9 Load Setup Defaults OnChip Primary/Secondary PCI IDE 6.10 Integrated PeripheralsIDE Prefetch Mode IDE HDD Block ModeOnboard FDD Controller UART 2 ModeOnboard Parallel Mode IDE Primary/Secondary Master/Slave UDMAChapter 7 LANDesk User Guide 6.11 Supervisor / User PasswordChapter 7 LANDesk User Guide 6.12 IDE HDD Auto Detection6.13 HDD Low Level Format Chapter 7 LANDesk User Guide 6.14 Save & Exit Setup6.15 Exit Without Saving

Bank0

Bank1

Total Memory

(SIMM1, SIMM2)

(SIMM3, SIMM4)