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AI5VG user manual
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AI5VG
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Specifications
Install
BIOS Configuration
Wire Color
Reset Switch: Pins 9 and
BIOS Setup
Load BIOS Defaults
Typematic Delay Msec
Signal Name
Hardware Settings
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Contents
Pentium VP3 Baby AT Motherboard
AI5VG
User’s Manual
Page
Contents
Chapter 4 Hardware Settings
Chapter 6 BIOS Configuration
•Introduction •Specifications
Checklist
Chapter 1 Introduction
•Hardware Description •Hardware Settings
L2 Cache
Chapter 2 Specifications
Main Processor
Main Memory
Onboard Bus Mastering EIDE
BIOS
CPU Temperature Sensor
Windows 95 Shut-Down
Chapter 3 Hardware Description
Figure 1: Layout of the AI5VG Motherboard
Chapter 3 Hardware Description
3.3 Main Memory
3.1 Processor and CPU Voltage
3.2 L2 Cache Memory
Chapter 3 Hardware Description
Total Memory
Bank0
Bank1
SIMM1, SIMM2
Bank1 DIMM1
3.4 BIOS
Bank0 DIMM2
Total Memory
3.6 Onboard Multi-I/O
3.7 Onboard CPU Temperature Sensor
3.5 Onboard PCI EIDE
3. Power Management
Address
3.8 I/O Port Address Map
3.9 DMA Channels
Device Description
Level
3.10 Interrupt Request Lines IRQ
3.11 Accelerated Graphics Port AGP Slot
Function
Chapter 4 Hardware Settings
Figure 2: Jumper Locations of the AI5VG
Chapter 4 Hardware Settings
CPU FREQ
Bus Clock
Mutiplier
P55C = Pentium with MMX technology
CPU FREQ
Bus Clock
Mutiplier
Bus Clock
Intel P55C, Cyrix 6x86L/MX, AMD K6
4.2 SW21-4:CPU Voltage Selector
For Dual Voltage CPU
Bus Clock
3.3V
Function
4.3 JP5: Clear CMOS Selection
Function
Chapter 5 Installation
Figure 3: Connector Location on the AI5VG
Chapter 5 Installation
5.2 J3: AT Power Supply Connector
5.1 I/O Connectors
Figure 4: Orientation of the I/O Connector
Wire Color
Signal Name
5.3 J2: ATX Power Supply Connector
5.4 J1, J4: AT Keyboard and PS/2 Mouse Connectors
Signal Name
Signal Name
5.6 J8: Floppy Drive Connector
5.5 J7, J6: Serial Ports
Signal Name
Signal Name
5.7 J9, J11: EIDE Connectors
J9: Primary IDE Connector
Signal Name
5.10 J5: USB Connector
5.8 J10: Parallel Port Connector
5.9 J15: IrDA Connector
Signal Name
5.13 J20 Front Bezel Connector
5.11 J13 Wake on LAN Connector
5.12 J14: CPU Fan Power Connector
Pin # Signal Name
Power LED and Keylock: Pins 11 -
Speaker: Pins 1 -
Signal Name
Signal Name
J20 Pin #
Reset Switch: Pins 9 and
Signal Name
Chapter 6 BIOS Configuration
Cache Rd+CPU Wt Pipeline
IDE Primary/Secondary Master/Slave PIO
Press <DEL> to Enter Setup
6.1 BIOS Introduction
6.2 BIOS Setup
STANDARD CMOS SETUP
Chapter 7 LANDesk User Guide
6.3 Standard CMOS Setup
Date
Primary HDDs / Secondary HDDs
MODE for IDE HDD only : Auto
Time
CYLS
Video
Floppy 3 Mode Support
Drive A / Drive B
Halt On
CPU Internal Cache / External Cache
6.4 BIOS Features Setup
Virus Warning
Boot Up Floppy Seek
Quick Power On Self Test
Boot Sequence
Boot Up NumLock Status
Video BIOS Shadow
Typematic Rate Setting
Typematic Delay Msec
Typematic Rate Chars/Sec
DRAM Read Pipeline
6.5 Chipset Features Setup
Bank DRAM Timing
Sustained 3T Write
Cache Timing
Video BIOS Cacheable
System BIOS Cacheable
Memory Hole at 15MB Addr
6.6 Power Management Setup
Power Management
Suspend Mode
HDD Power Down
Doze Mode
PM Control by APM
PM Events
Chapter 7 LANDesk User Guide
Reset Configuration Data
6.7 PNP/PCI Configuration
PNP OS Installed
Resources Controlled by
CPU to PCI Write Buffer
PCI Delay Transaction
PCI#2 Access #1 Retry
PCI Dynamic Bursting
PCI IDE IRQ Map To
Chapter 7 LANDesk User Guide
Chapter 7 LANDesk User Guide
6.8 Load BIOS Defaults
6.9 Load Setup Defaults
IDE HDD Block Mode
6.10 Integrated Peripherals
IDE Prefetch Mode
OnChip Primary/Secondary PCI IDE
IDE Primary/Secondary Master/Slave UDMA
UART 2 Mode
Onboard Parallel Mode
Onboard FDD Controller
6.11 Supervisor / User Password
Chapter 7 LANDesk User Guide
Chapter 7 LANDesk User Guide
6.12 IDE HDD Auto Detection
6.13 HDD Low Level Format
Chapter 7 LANDesk User Guide
6.14 Save & Exit Setup
6.15 Exit Without Saving
