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Intel AI5VG user manual Contents, Hardware Settings

Models: AI5VG

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Contents

		Contents
	Contents
Chapter 1 Introduction		1
Chapter 2 Specifications		2
Chapter 3 Hardware Description		4
3.1	Processor and CPU Voltage	6
3.2	L2 Cache Memory	6
3.3	Main Memory	6
3.4	BIOS	8
3.5	Onboard PCI EIDE	9
3.6	Onboard Multi-I/O	9
3.7	Onboard CPU Temperature Sensor	9
3.8	I/O Port Address Map	10
3.9	DMA Channels	10
3.10	Interrupt Request Lines (IRQ)	11
3.11	Accelerated Graphics Port (AGP) Slot	11
Chapter 4 Hardware Settings		12
4.1	SW1(1-8): CPU Frequency Selector	14
4.2	SW2(1-4): CPU Voltage Selector	16
4.3	JP5: Clear CMOS Selection	18
Chapter 5 Installation		19
5.1	I/O Connectors	21
5.2	J3: AT Power Supply Connector	21
5.3	J2: ATX Power Supply Connector	22
5.4	J1, J4: AT Keyboard and PS/2 Mouse Connectors	22
5.5	J7, J6: Serial Ports	23
5.6	J8: Floppy Drive Connector	23
5.7	J9, J11: EIDE Connectors	24
5.8	J10: Parallel Port Connector	25
5.9	J15: IrDA Connector	25
5.10 J5: USB Connector		25
5.11 J13 Wake on LAN Connector		26
5.12 J14: CPU Fan Power Connector		26
5.13 J20 Front Bezel Connector		26
AI5VG Pentium VP3 Baby AT Motherboard User’s Manual		i

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Intel AI5VG user manual Contents, Hardware Settings

Contents

AI5VG User’s ManualPentium VP3 Baby AT Motherboard Page Chapter 4 Hardware Settings ContentsChapter 6 BIOS Configuration •Hardware Description •Hardware Settings ChecklistChapter 1 Introduction •Introduction •SpecificationsMain Memory Chapter 2 SpecificationsMain Processor L2 CacheWindows 95 Shut-Down BIOSCPU Temperature Sensor Onboard Bus Mastering EIDEChapter 3 Hardware Description Chapter 3 Hardware Description Figure 1: Layout of the AI5VG MotherboardChapter 3 Hardware Description 3.1 Processor and CPU Voltage3.2 L2 Cache Memory 3.3 Main MemorySIMM1, SIMM2 Bank0Bank1 Total MemoryTotal Memory 3.4 BIOSBank0 DIMM2 Bank1 DIMM13. Power Management 3.7 Onboard CPU Temperature Sensor3.5 Onboard PCI EIDE 3.6 Onboard Multi-I/ODevice Description 3.8 I/O Port Address Map3.9 DMA Channels AddressFunction 3.10 Interrupt Request Lines IRQ3.11 Accelerated Graphics Port AGP Slot LevelChapter 4 Hardware Settings Chapter 4 Hardware Settings Figure 2: Jumper Locations of the AI5VGP55C = Pentium with MMX technology Bus ClockMutiplier CPU FREQBus Clock Bus ClockMutiplier CPU FREQBus Clock 4.2 SW21-4:CPU Voltage SelectorFor Dual Voltage CPU Intel P55C, Cyrix 6x86L/MX, AMD K63.3V 4.3 JP5: Clear CMOS Selection FunctionFunction Chapter 5 Installation Chapter 5 Installation Figure 3: Connector Location on the AI5VGWire Color 5.1 I/O ConnectorsFigure 4: Orientation of the I/O Connector 5.2 J3: AT Power Supply ConnectorSignal Name 5.3 J2: ATX Power Supply Connector5.4 J1, J4: AT Keyboard and PS/2 Mouse Connectors Signal NameSignal Name 5.6 J8: Floppy Drive Connector5.5 J7, J6: Serial Ports Signal NameSignal Name 5.7 J9, J11: EIDE ConnectorsJ9: Primary IDE Connector Signal NameSignal Name 5.8 J10: Parallel Port Connector5.9 J15: IrDA Connector 5.10 J5: USB ConnectorPin # Signal Name 5.11 J13 Wake on LAN Connector5.12 J14: CPU Fan Power Connector 5.13 J20 Front Bezel ConnectorSignal Name Speaker: Pins 1 -Signal Name Power LED and Keylock: Pins 11 -Reset Switch: Pins 9 and Signal NameJ20 Pin # Chapter 6 BIOS Configuration Cache Rd+CPU Wt Pipeline IDE Primary/Secondary Master/Slave PIO 6.1 BIOS Introduction 6.2 BIOS SetupPress <DEL> to Enter Setup Chapter 7 LANDesk User Guide STANDARD CMOS SETUPDate 6.3 Standard CMOS SetupCYLS MODE for IDE HDD only : AutoTime Primary HDDs / Secondary HDDsHalt On Floppy 3 Mode SupportDrive A / Drive B Video6.4 BIOS Features Setup Virus WarningCPU Internal Cache / External Cache Boot Up NumLock Status Quick Power On Self TestBoot Sequence Boot Up Floppy SeekTypematic Rate Chars/Sec Typematic Rate SettingTypematic Delay Msec Video BIOS ShadowSustained 3T Write 6.5 Chipset Features SetupBank DRAM Timing DRAM Read PipelineMemory Hole at 15MB Addr Video BIOS CacheableSystem BIOS Cacheable Cache TimingPower Management 6.6 Power Management SetupPM Control by APM HDD Power DownDoze Mode Suspend ModeChapter 7 LANDesk User Guide PM EventsResources Controlled by 6.7 PNP/PCI ConfigurationPNP OS Installed Reset Configuration DataPCI Dynamic Bursting PCI Delay TransactionPCI#2 Access #1 Retry CPU to PCI Write BufferChapter 7 LANDesk User Guide PCI IDE IRQ Map To6.8 Load BIOS Defaults 6.9 Load Setup DefaultsChapter 7 LANDesk User Guide OnChip Primary/Secondary PCI IDE 6.10 Integrated PeripheralsIDE Prefetch Mode IDE HDD Block ModeOnboard FDD Controller UART 2 ModeOnboard Parallel Mode IDE Primary/Secondary Master/Slave UDMAChapter 7 LANDesk User Guide 6.11 Supervisor / User Password6.12 IDE HDD Auto Detection 6.13 HDD Low Level FormatChapter 7 LANDesk User Guide 6.14 Save & Exit Setup 6.15 Exit Without SavingChapter 7 LANDesk User Guide