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Intel AI5VG user manual Cache Rd+CPU Wt Pipeline

Models: AI5VG

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Chapter 7 LANDesk User Guide
Cache Rd+CPU Wt Pipeline
Read Around Write
Cache Timing
Video BIOS Cacheable
System BIOS Cacheable
Memory Hole at 15MB Addr.
AGP
Aperture Size
OnChip USB
6.6 Power Management Setup	42
Power Management
PM Control by APM
Video Off Method
Modem Use IRQ
Soft-Off by PWRBTN
HDD Power Down
Doze Mode
Suspend Mode
PM Events

6.7PNP/PCI Configuration PNP OS Installed Resources Controlled by Reset Configuration Data

IRQ3/4/5/7/9/10/11/12/14/15, DMA0/1/3/5/6/7 assigned to CPU to PCI Write Buffer

PCI Dynamic Bursting PCI Master 0 WS Write PCI Delay Transaction PCI Master Read Prefetch PCI#2 Access #1 Retry PCI Master 1 WS Write PCI Master 1 WS Read PCI IRQ Activated by PCI IDE IRQ Map To

6.8	Load BIOS Defaults	48
6.9	Load Setup Defaults	48
6.10	Integrated Peripherals	49
	OnChip Primary/Secondary PCI IDE
	IDE Prefetch Mode
	IDE HDD Block Mode
30	AI5VG Pentium VP3 Baby AT Motherboard User’s Manual

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Intel AI5VG user manual Cache Rd+CPU Wt Pipeline

Contents

User’s Manual AI5VGPentium VP3 Baby AT Motherboard Page Contents Chapter 4 Hardware SettingsChapter 6 BIOS Configuration •Introduction •Specifications ChecklistChapter 1 Introduction •Hardware Description •Hardware SettingsL2 Cache Chapter 2 SpecificationsMain Processor Main MemoryOnboard Bus Mastering EIDE BIOSCPU Temperature Sensor Windows 95 Shut-DownChapter 3 Hardware Description Figure 1: Layout of the AI5VG Motherboard Chapter 3 Hardware Description3.3 Main Memory 3.1 Processor and CPU Voltage3.2 L2 Cache Memory Chapter 3 Hardware DescriptionTotal Memory Bank0Bank1 SIMM1, SIMM2Bank1 DIMM1 3.4 BIOSBank0 DIMM2 Total Memory3.6 Onboard Multi-I/O 3.7 Onboard CPU Temperature Sensor3.5 Onboard PCI EIDE 3. Power ManagementAddress 3.8 I/O Port Address Map3.9 DMA Channels Device DescriptionLevel 3.10 Interrupt Request Lines IRQ3.11 Accelerated Graphics Port AGP Slot FunctionChapter 4 Hardware Settings Figure 2: Jumper Locations of the AI5VG Chapter 4 Hardware SettingsCPU FREQ Bus ClockMutiplier P55C = Pentium with MMX technologyCPU FREQ Bus ClockMutiplier Bus ClockIntel P55C, Cyrix 6x86L/MX, AMD K6 4.2 SW21-4:CPU Voltage SelectorFor Dual Voltage CPU Bus Clock3.3V Function 4.3 JP5: Clear CMOS SelectionFunction Chapter 5 Installation Figure 3: Connector Location on the AI5VG Chapter 5 Installation5.2 J3: AT Power Supply Connector 5.1 I/O ConnectorsFigure 4: Orientation of the I/O Connector Wire ColorSignal Name 5.3 J2: ATX Power Supply Connector5.4 J1, J4: AT Keyboard and PS/2 Mouse Connectors Signal NameSignal Name 5.6 J8: Floppy Drive Connector5.5 J7, J6: Serial Ports Signal NameSignal Name 5.7 J9, J11: EIDE ConnectorsJ9: Primary IDE Connector Signal Name5.10 J5: USB Connector 5.8 J10: Parallel Port Connector5.9 J15: IrDA Connector Signal Name5.13 J20 Front Bezel Connector 5.11 J13 Wake on LAN Connector5.12 J14: CPU Fan Power Connector Pin # Signal NamePower LED and Keylock: Pins 11 - Speaker: Pins 1 -Signal Name Signal NameSignal Name Reset Switch: Pins 9 andJ20 Pin # Chapter 6 BIOS Configuration Cache Rd+CPU Wt Pipeline IDE Primary/Secondary Master/Slave PIO 6.2 BIOS Setup 6.1 BIOS IntroductionPress <DEL> to Enter Setup STANDARD CMOS SETUP Chapter 7 LANDesk User Guide6.3 Standard CMOS Setup DatePrimary HDDs / Secondary HDDs MODE for IDE HDD only : AutoTime CYLSVideo Floppy 3 Mode SupportDrive A / Drive B Halt OnVirus Warning 6.4 BIOS Features SetupCPU Internal Cache / External Cache Boot Up Floppy Seek Quick Power On Self TestBoot Sequence Boot Up NumLock StatusVideo BIOS Shadow Typematic Rate SettingTypematic Delay Msec Typematic Rate Chars/SecDRAM Read Pipeline 6.5 Chipset Features SetupBank DRAM Timing Sustained 3T WriteCache Timing Video BIOS CacheableSystem BIOS Cacheable Memory Hole at 15MB Addr6.6 Power Management Setup Power ManagementSuspend Mode HDD Power DownDoze Mode PM Control by APMPM Events Chapter 7 LANDesk User GuideReset Configuration Data 6.7 PNP/PCI ConfigurationPNP OS Installed Resources Controlled byCPU to PCI Write Buffer PCI Delay TransactionPCI#2 Access #1 Retry PCI Dynamic BurstingPCI IDE IRQ Map To Chapter 7 LANDesk User Guide6.9 Load Setup Defaults 6.8 Load BIOS DefaultsChapter 7 LANDesk User Guide IDE HDD Block Mode 6.10 Integrated PeripheralsIDE Prefetch Mode OnChip Primary/Secondary PCI IDEIDE Primary/Secondary Master/Slave UDMA UART 2 ModeOnboard Parallel Mode Onboard FDD Controller6.11 Supervisor / User Password Chapter 7 LANDesk User Guide6.13 HDD Low Level Format 6.12 IDE HDD Auto DetectionChapter 7 LANDesk User Guide 6.15 Exit Without Saving 6.14 Save & Exit SetupChapter 7 LANDesk User Guide