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user manual Connector Location on the AI5VG, Installation
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AI5VG
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Specification
Install
6.7 PNP/PCI Configuration
Wire Color
Press <DEL> to Enter Setup
Signal Name
Hardware Settings
Load BIOS Defaults
Power Management
BIOS Configuration
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Chapter 5 Installation
Figure 3: Connector Location on the AI5VG
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AI5VG Pentium VP3 Baby AT Motherboard User’s Manual
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Contents
AI5VG
User’s Manual
Pentium VP3 Baby AT Motherboard
Page
Contents
Chapter 4 Hardware Settings
Chapter 6 BIOS Configuration
Checklist
Chapter 1 Introduction
•Introduction •Specifications
•Hardware Description •Hardware Settings
Chapter 2 Specifications
Main Processor
L2 Cache
Main Memory
BIOS
Onboard Bus Mastering EIDE
CPU Temperature Sensor
Windows 95 Shut-Down
Chapter 3 Hardware Description
Figure 1: Layout of the AI5VG Motherboard
Chapter 3 Hardware Description
3.1 Processor and CPU Voltage
3.2 L2 Cache Memory
3.3 Main Memory
Chapter 3 Hardware Description
Bank0
Bank1
Total Memory
SIMM1, SIMM2
3.4 BIOS
Bank0 DIMM2
Bank1 DIMM1
Total Memory
3.5 Onboard PCI EIDE
3.6 Onboard Multi-I/O
3.7 Onboard CPU Temperature Sensor
3. Power Management
3.8 I/O Port Address Map
3.9 DMA Channels
Address
Device Description
3.10 Interrupt Request Lines IRQ
3.11 Accelerated Graphics Port AGP Slot
Level
Function
Chapter 4 Hardware Settings
Figure 2: Jumper Locations of the AI5VG
Chapter 4 Hardware Settings
Bus Clock
Mutiplier
CPU FREQ
P55C = Pentium with MMX technology
Bus Clock
Mutiplier
CPU FREQ
Bus Clock
4.2 SW21-4:CPU Voltage Selector
For Dual Voltage CPU
Intel P55C, Cyrix 6x86L/MX, AMD K6
Bus Clock
3.3V
4.3 JP5: Clear CMOS Selection
Function
Function
Chapter 5 Installation
Figure 3: Connector Location on the AI5VG
Chapter 5 Installation
5.1 I/O Connectors
Figure 4: Orientation of the I/O Connector
5.2 J3: AT Power Supply Connector
Wire Color
5.3 J2: ATX Power Supply Connector
5.4 J1, J4: AT Keyboard and PS/2 Mouse Connectors
Signal Name
Signal Name
5.6 J8: Floppy Drive Connector
5.5 J7, J6: Serial Ports
Signal Name
Signal Name
5.7 J9, J11: EIDE Connectors
J9: Primary IDE Connector
Signal Name
Signal Name
5.8 J10: Parallel Port Connector
5.9 J15: IrDA Connector
5.10 J5: USB Connector
Signal Name
5.11 J13 Wake on LAN Connector
5.12 J14: CPU Fan Power Connector
5.13 J20 Front Bezel Connector
Pin # Signal Name
Speaker: Pins 1 -
Signal Name
Power LED and Keylock: Pins 11 -
Signal Name
Reset Switch: Pins 9 and
Signal Name
J20 Pin #
Chapter 6 BIOS Configuration
Cache Rd+CPU Wt Pipeline
IDE Primary/Secondary Master/Slave PIO
6.1 BIOS Introduction
6.2 BIOS Setup
Press <DEL> to Enter Setup
STANDARD CMOS SETUP
Chapter 7 LANDesk User Guide
6.3 Standard CMOS Setup
Date
Time
Primary HDDs / Secondary HDDs
CYLS
HEAD
Drive A / Drive B
Floppy 3 Mode Support
Video
Halt On
6.4 BIOS Features Setup
Virus Warning
CPU Internal Cache / External Cache
Quick Power On Self Test
Boot Sequence
Boot Up Floppy Seek
Boot Up NumLock Status
Typematic Rate Setting
Video BIOS Shadow
Typematic Rate Chars/Sec
Typematic Delay Msec
6.5 Chipset Features Setup
Bank DRAM Timing
DRAM Read Pipeline
Sustained 3T Write
Video BIOS Cacheable
System BIOS Cacheable
Cache Timing
Memory Hole at 15MB Addr
6.6 Power Management Setup
Power Management
HDD Power Down
PM Control by APM
Video Off Method
Modem Use IRQ
PM Events
Chapter 7 LANDesk User Guide
6.7 PNP/PCI Configuration
PNP OS Installed
Reset Configuration Data
Resources Controlled by
PCI#2 Access #1 Retry
CPU to PCI Write Buffer
PCI Dynamic Bursting
PCI Master 0 WS Write
PCI IDE IRQ Map To
Chapter 7 LANDesk User Guide
6.8 Load BIOS Defaults
6.9 Load Setup Defaults
Chapter 7 LANDesk User Guide
6.10 Integrated Peripherals
OnChip Primary/Secondary PCI IDE
IDE Prefetch Mode
IDE HDD Block Mode
IDE Primary/Secondary Master/Slave UDMA
Onboard FDD Controller
Onboard Serial/Parallel Port
UART 2 Mode
6.11 Supervisor / User Password
Chapter 7 LANDesk User Guide
6.12 IDE HDD Auto Detection
6.13 HDD Low Level Format
Chapter 7 LANDesk User Guide
6.14 Save & Exit Setup
6.15 Exit Without Saving
Chapter 7 LANDesk User Guide
